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7b4e58440f
T4240 PCIe IP is version 3.0 and has some update comparing previous QorIQ products. 1. Move Freescale specific register define to arch/powerpc/include/asm/fsl_pci.h and update the register offset define for T4240. 2. add the status/control register define use status/control register to judge the link status 3. The original code uses 'Programming Interface' field to judge if PCIE is EP or RC mode, however, T4240 does not support this functionality. According to PCIE specification, 'Header Type' offset 0x0e is used to indicate header type, so for PCIE controller, the patch changes code to use 'Header Type' field to identify if the PCIE is RC or EP mode. This patch fixes the PCIe card link up issue on T4240QDS. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com>
289 lines
10 KiB
C
289 lines
10 KiB
C
/*
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* Copyright 2007,2009-2012 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __FSL_PCI_H_
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#define __FSL_PCI_H_
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#include <asm/fsl_law.h>
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#include <asm/fsl_serdes.h>
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#include <pci.h>
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#define PEX_IP_BLK_REV_2_2 0x02080202
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#define PEX_IP_BLK_REV_2_3 0x02080203
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#define PEX_IP_BLK_REV_3_0 0x02080300
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/* Freescale-specific PCI config registers */
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#define FSL_PCI_PBFR 0x44
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#ifdef CONFIG_SYS_FSL_PCI_VER_3_X
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/* Currently only the PCIe capability is used, so hardcode the offset.
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* if more capabilities need to be justified, the capability link method
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* should be applied here
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*/
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#define FSL_PCIE_CAP_ID 0x70
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#define PCI_DCR 0x78 /* PCIe Device Control Register */
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#define PCI_DSR 0x7a /* PCIe Device Status Register */
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#define PCI_LSR 0x82 /* PCIe Link Status Register */
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#define PCI_LCR 0x80 /* PCIe Link Control Register */
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#else
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#define FSL_PCIE_CAP_ID 0x4c
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#define PCI_DCR 0x54 /* PCIe Device Control Register */
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#define PCI_DSR 0x56 /* PCIe Device Status Register */
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#define PCI_LSR 0x5e /* PCIe Link Status Register */
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#define PCI_LCR 0x5c /* PCIe Link Control Register */
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#endif
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#define FSL_PCIE_CFG_RDY 0x4b0
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#define FSL_PROG_IF_AGENT 0x1
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#define PCI_LTSSM 0x404 /* PCIe Link Training, Status State Machine */
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#define PCI_LTSSM_L0 0x16 /* L0 state */
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int fsl_setup_hose(struct pci_controller *hose, unsigned long addr);
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int fsl_is_pci_agent(struct pci_controller *hose);
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void fsl_pci_config_unlock(struct pci_controller *hose);
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void ft_fsl_pci_setup(void *blob, const char *compat, unsigned long ctrl_addr);
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/*
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* Common PCI/PCIE Register structure for mpc85xx and mpc86xx
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*/
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/*
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* PCI Translation Registers
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*/
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typedef struct pci_outbound_window {
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u32 potar; /* 0x00 - Address */
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u32 potear; /* 0x04 - Address Extended */
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u32 powbar; /* 0x08 - Window Base Address */
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u32 res1;
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u32 powar; /* 0x10 - Window Attributes */
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#define POWAR_EN 0x80000000
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#define POWAR_IO_READ 0x00080000
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#define POWAR_MEM_READ 0x00040000
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#define POWAR_IO_WRITE 0x00008000
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#define POWAR_MEM_WRITE 0x00004000
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u32 res2[3];
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} pot_t;
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typedef struct pci_inbound_window {
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u32 pitar; /* 0x00 - Address */
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u32 res1;
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u32 piwbar; /* 0x08 - Window Base Address */
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u32 piwbear; /* 0x0c - Window Base Address Extended */
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u32 piwar; /* 0x10 - Window Attributes */
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#define PIWAR_EN 0x80000000
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#define PIWAR_PF 0x20000000
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#define PIWAR_LOCAL 0x00f00000
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#define PIWAR_READ_SNOOP 0x00050000
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#define PIWAR_WRITE_SNOOP 0x00005000
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u32 res2[3];
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} pit_t;
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/* PCI/PCI Express Registers */
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typedef struct ccsr_pci {
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u32 cfg_addr; /* 0x000 - PCI Configuration Address Register */
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u32 cfg_data; /* 0x004 - PCI Configuration Data Register */
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u32 int_ack; /* 0x008 - PCI Interrupt Acknowledge Register */
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u32 out_comp_to; /* 0x00C - PCI Outbound Completion Timeout Register */
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u32 out_conf_to; /* 0x010 - PCI Configuration Timeout Register */
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u32 config; /* 0x014 - PCIE CONFIG Register */
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u32 int_status; /* 0x018 - PCIE interrupt status register */
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char res2[4];
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u32 pme_msg_det; /* 0x020 - PCIE PME & message detect register */
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u32 pme_msg_dis; /* 0x024 - PCIE PME & message disable register */
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u32 pme_msg_int_en; /* 0x028 - PCIE PME & message interrupt enable register */
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u32 pm_command; /* 0x02c - PCIE PM Command register */
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char res4[3016]; /* (- #xbf8 #x30)3016 */
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u32 block_rev1; /* 0xbf8 - PCIE Block Revision register 1 */
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u32 block_rev2; /* 0xbfc - PCIE Block Revision register 2 */
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pot_t pot[5]; /* 0xc00 - 0xc9f Outbound ATMU's 0, 1, 2, 3, and 4 */
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u32 res5[24];
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pit_t pmit; /* 0xd00 - 0xd9c Inbound ATMU's MSI */
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u32 res6[24];
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pit_t pit[4]; /* 0xd80 - 0xdff Inbound ATMU's 3, 2, 1 and 0 */
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#define PIT3 0
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#define PIT2 1
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#define PIT1 2
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#if 0
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u32 potar0; /* 0xc00 - PCI Outbound Transaction Address Register 0 */
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u32 potear0; /* 0xc04 - PCI Outbound Translation Extended Address Register 0 */
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char res5[8];
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u32 powar0; /* 0xc10 - PCI Outbound Window Attributes Register 0 */
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char res6[12];
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u32 potar1; /* 0xc20 - PCI Outbound Transaction Address Register 1 */
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u32 potear1; /* 0xc24 - PCI Outbound Translation Extended Address Register 1 */
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u32 powbar1; /* 0xc28 - PCI Outbound Window Base Address Register 1 */
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char res7[4];
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u32 powar1; /* 0xc30 - PCI Outbound Window Attributes Register 1 */
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char res8[12];
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u32 potar2; /* 0xc40 - PCI Outbound Transaction Address Register 2 */
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u32 potear2; /* 0xc44 - PCI Outbound Translation Extended Address Register 2 */
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u32 powbar2; /* 0xc48 - PCI Outbound Window Base Address Register 2 */
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char res9[4];
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u32 powar2; /* 0xc50 - PCI Outbound Window Attributes Register 2 */
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char res10[12];
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u32 potar3; /* 0xc60 - PCI Outbound Transaction Address Register 3 */
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u32 potear3; /* 0xc64 - PCI Outbound Translation Extended Address Register 3 */
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u32 powbar3; /* 0xc68 - PCI Outbound Window Base Address Register 3 */
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char res11[4];
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u32 powar3; /* 0xc70 - PCI Outbound Window Attributes Register 3 */
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char res12[12];
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u32 potar4; /* 0xc80 - PCI Outbound Transaction Address Register 4 */
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u32 potear4; /* 0xc84 - PCI Outbound Translation Extended Address Register 4 */
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u32 powbar4; /* 0xc88 - PCI Outbound Window Base Address Register 4 */
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char res13[4];
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u32 powar4; /* 0xc90 - PCI Outbound Window Attributes Register 4 */
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char res14[268];
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u32 pitar3; /* 0xda0 - PCI Inbound Translation Address Register 3 */
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char res15[4];
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u32 piwbar3; /* 0xda8 - PCI Inbound Window Base Address Register 3 */
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u32 piwbear3; /* 0xdac - PCI Inbound Window Base Extended Address Register 3 */
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u32 piwar3; /* 0xdb0 - PCI Inbound Window Attributes Register 3 */
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char res16[12];
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u32 pitar2; /* 0xdc0 - PCI Inbound Translation Address Register 2 */
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char res17[4];
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u32 piwbar2; /* 0xdc8 - PCI Inbound Window Base Address Register 2 */
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u32 piwbear2; /* 0xdcc - PCI Inbound Window Base Extended Address Register 2 */
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u32 piwar2; /* 0xdd0 - PCI Inbound Window Attributes Register 2 */
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char res18[12];
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u32 pitar1; /* 0xde0 - PCI Inbound Translation Address Register 1 */
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char res19[4];
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u32 piwbar1; /* 0xde8 - PCI Inbound Window Base Address Register 1 */
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char res20[4];
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u32 piwar1; /* 0xdf0 - PCI Inbound Window Attributes Register 1 */
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char res21[12];
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#endif
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u32 pedr; /* 0xe00 - PCI Error Detect Register */
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u32 pecdr; /* 0xe04 - PCI Error Capture Disable Register */
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u32 peer; /* 0xe08 - PCI Error Interrupt Enable Register */
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u32 peattrcr; /* 0xe0c - PCI Error Attributes Capture Register */
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u32 peaddrcr; /* 0xe10 - PCI Error Address Capture Register */
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/* u32 perr_disr * 0xe10 - PCIE Erorr Disable Register */
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u32 peextaddrcr; /* 0xe14 - PCI Error Extended Address Capture Register */
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u32 pedlcr; /* 0xe18 - PCI Error Data Low Capture Register */
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u32 pedhcr; /* 0xe1c - PCI Error Error Data High Capture Register */
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u32 gas_timr; /* 0xe20 - PCI Gasket Timer Register */
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/* u32 perr_cap_stat; * 0xe20 - PCIE Error Capture Status Register */
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char res22[4];
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u32 perr_cap0; /* 0xe28 - PCIE Error Capture Register 0 */
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u32 perr_cap1; /* 0xe2c - PCIE Error Capture Register 1 */
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u32 perr_cap2; /* 0xe30 - PCIE Error Capture Register 2 */
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u32 perr_cap3; /* 0xe34 - PCIE Error Capture Register 3 */
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char res23[200];
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u32 pdb_stat; /* 0xf00 - PCIE Debug Status */
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char res24[16];
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u32 pex_csr0; /* 0xf14 - PEX Control/Status register 0*/
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u32 pex_csr1; /* 0xf18 - PEX Control/Status register 1*/
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char res25[228];
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} ccsr_fsl_pci_t;
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#define PCIE_CONFIG_PC 0x00020000
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#define PCIE_CONFIG_OB_CK 0x00002000
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#define PCIE_CONFIG_SAC 0x00000010
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#define PCIE_CONFIG_SP 0x80000002
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#define PCIE_CONFIG_SCC 0x80000001
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struct fsl_pci_info {
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unsigned long regs;
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pci_addr_t mem_bus;
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phys_size_t mem_phys;
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pci_size_t mem_size;
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pci_addr_t io_bus;
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phys_size_t io_phys;
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pci_size_t io_size;
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enum law_trgt_if law;
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int pci_num;
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};
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void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info);
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int fsl_pci_init_port(struct fsl_pci_info *pci_info,
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struct pci_controller *hose, int busno);
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int fsl_pcie_init_ctrl(int busno, u32 devdisr, enum srds_prtcl dev,
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struct fsl_pci_info *pci_info);
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int fsl_pcie_init_board(int busno);
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#define SET_STD_PCI_INFO(x, num) \
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{ \
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x.regs = CONFIG_SYS_PCI##num##_ADDR; \
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x.mem_bus = CONFIG_SYS_PCI##num##_MEM_BUS; \
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x.mem_phys = CONFIG_SYS_PCI##num##_MEM_PHYS; \
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x.mem_size = CONFIG_SYS_PCI##num##_MEM_SIZE; \
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x.io_bus = CONFIG_SYS_PCI##num##_IO_BUS; \
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x.io_phys = CONFIG_SYS_PCI##num##_IO_PHYS; \
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x.io_size = CONFIG_SYS_PCI##num##_IO_SIZE; \
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x.law = LAW_TRGT_IF_PCI_##num; \
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x.pci_num = num; \
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}
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#define SET_STD_PCIE_INFO(x, num) \
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{ \
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x.regs = CONFIG_SYS_PCIE##num##_ADDR; \
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x.mem_bus = CONFIG_SYS_PCIE##num##_MEM_BUS; \
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x.mem_phys = CONFIG_SYS_PCIE##num##_MEM_PHYS; \
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x.mem_size = CONFIG_SYS_PCIE##num##_MEM_SIZE; \
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x.io_bus = CONFIG_SYS_PCIE##num##_IO_BUS; \
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x.io_phys = CONFIG_SYS_PCIE##num##_IO_PHYS; \
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x.io_size = CONFIG_SYS_PCIE##num##_IO_SIZE; \
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x.law = LAW_TRGT_IF_PCIE_##num; \
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x.pci_num = num; \
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}
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#define __FT_FSL_PCI_SETUP(blob, compat, num) \
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ft_fsl_pci_setup(blob, compat, CONFIG_SYS_PCI##num##_ADDR)
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#define __FT_FSL_PCIE_SETUP(blob, compat, num) \
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ft_fsl_pci_setup(blob, compat, CONFIG_SYS_PCIE##num##_ADDR)
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#define FT_FSL_PCI1_SETUP __FT_FSL_PCI_SETUP(blob, FSL_PCI_COMPAT, 1)
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#define FT_FSL_PCI2_SETUP __FT_FSL_PCI_SETUP(blob, FSL_PCI_COMPAT, 2)
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#define FT_FSL_PCIE1_SETUP __FT_FSL_PCIE_SETUP(blob, FSL_PCIE_COMPAT, 1)
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#define FT_FSL_PCIE2_SETUP __FT_FSL_PCIE_SETUP(blob, FSL_PCIE_COMPAT, 2)
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#define FT_FSL_PCIE3_SETUP __FT_FSL_PCIE_SETUP(blob, FSL_PCIE_COMPAT, 3)
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#define FT_FSL_PCIE4_SETUP __FT_FSL_PCIE_SETUP(blob, FSL_PCIE_COMPAT, 4)
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#if !defined(CONFIG_PCI)
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#define FT_FSL_PCI_SETUP
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#elif defined(CONFIG_FSL_CORENET)
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#define FSL_PCIE_COMPAT CONFIG_SYS_FSL_PCIE_COMPAT
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#define FT_FSL_PCI_SETUP \
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FT_FSL_PCIE1_SETUP; \
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FT_FSL_PCIE2_SETUP; \
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FT_FSL_PCIE3_SETUP; \
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FT_FSL_PCIE4_SETUP;
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#define FT_FSL_PCIE_SETUP FT_FSL_PCI_SETUP
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#elif defined(CONFIG_MPC85xx)
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#define FSL_PCI_COMPAT "fsl,mpc8540-pci"
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#ifdef CONFIG_SYS_FSL_PCIE_COMPAT
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#define FSL_PCIE_COMPAT CONFIG_SYS_FSL_PCIE_COMPAT
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#else
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#define FSL_PCIE_COMPAT "fsl,mpc8548-pcie"
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#endif
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#define FT_FSL_PCI_SETUP \
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FT_FSL_PCI1_SETUP; \
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FT_FSL_PCI2_SETUP; \
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FT_FSL_PCIE1_SETUP; \
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FT_FSL_PCIE2_SETUP; \
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FT_FSL_PCIE3_SETUP;
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#define FT_FSL_PCIE_SETUP \
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FT_FSL_PCIE1_SETUP; \
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FT_FSL_PCIE2_SETUP; \
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FT_FSL_PCIE3_SETUP;
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#elif defined(CONFIG_MPC86xx)
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#define FSL_PCI_COMPAT "fsl,mpc8610-pci"
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#define FSL_PCIE_COMPAT "fsl,mpc8641-pcie"
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#define FT_FSL_PCI_SETUP \
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FT_FSL_PCI1_SETUP; \
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FT_FSL_PCIE1_SETUP; \
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FT_FSL_PCIE2_SETUP;
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#else
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#error FT_FSL_PCI_SETUP not defined
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#endif
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#endif
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