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0ced26a494
The tests rely on a dummy driver to allocate and initialize the regmaps and the regmap fields using the managed API. The first test checks if the regmap config fields like width, reg_offset_shift, range specifiers, etc work. The second test checks if regmap fields behave properly (mask and shift are ok) by peeking into the regmap. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> Signed-off-by: Pratyush Yadav <p.yadav@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org>
387 lines
10 KiB
C
387 lines
10 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2015 Google, Inc
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*/
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#include <common.h>
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#include <dm.h>
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#include <log.h>
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#include <mapmem.h>
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#include <regmap.h>
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#include <syscon.h>
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#include <rand.h>
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#include <asm/test.h>
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#include <dm/test.h>
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#include <dm/devres.h>
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#include <linux/err.h>
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#include <test/test.h>
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#include <test/ut.h>
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/* Base test of register maps */
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static int dm_test_regmap_base(struct unit_test_state *uts)
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{
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struct udevice *dev;
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struct regmap *map;
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ofnode node;
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int i;
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ut_assertok(uclass_get_device(UCLASS_SYSCON, 0, &dev));
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map = syscon_get_regmap(dev);
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ut_assertok_ptr(map);
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ut_asserteq(1, map->range_count);
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ut_asserteq(0x10, map->ranges[0].start);
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ut_asserteq(16, map->ranges[0].size);
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ut_asserteq(0x10, map_to_sysmem(regmap_get_range(map, 0)));
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ut_assertok(uclass_get_device(UCLASS_SYSCON, 1, &dev));
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map = syscon_get_regmap(dev);
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ut_assertok_ptr(map);
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ut_asserteq(4, map->range_count);
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ut_asserteq(0x20, map->ranges[0].start);
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for (i = 0; i < 4; i++) {
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const unsigned long addr = 0x20 + 8 * i;
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ut_asserteq(addr, map->ranges[i].start);
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ut_asserteq(5 + i, map->ranges[i].size);
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ut_asserteq(addr, map_to_sysmem(regmap_get_range(map, i)));
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}
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/* Check that we can't pretend a different device is a syscon */
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ut_assertok(uclass_get_device(UCLASS_I2C, 0, &dev));
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map = syscon_get_regmap(dev);
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ut_asserteq_ptr(ERR_PTR(-ENOEXEC), map);
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/* A different device can be a syscon by using Linux-compat API */
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node = ofnode_path("/syscon@2");
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ut_assert(ofnode_valid(node));
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map = syscon_node_to_regmap(node);
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ut_assertok_ptr(map);
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ut_asserteq(4, map->range_count);
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ut_asserteq(0x40, map->ranges[0].start);
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for (i = 0; i < 4; i++) {
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const unsigned long addr = 0x40 + 8 * i;
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ut_asserteq(addr, map->ranges[i].start);
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ut_asserteq(5 + i, map->ranges[i].size);
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ut_asserteq(addr, map_to_sysmem(regmap_get_range(map, i)));
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}
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return 0;
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}
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DM_TEST(dm_test_regmap_base, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
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/* Test we can access a regmap through syscon */
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static int dm_test_regmap_syscon(struct unit_test_state *uts)
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{
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struct regmap *map;
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map = syscon_get_regmap_by_driver_data(SYSCON0);
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ut_assertok_ptr(map);
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ut_asserteq(1, map->range_count);
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map = syscon_get_regmap_by_driver_data(SYSCON1);
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ut_assertok_ptr(map);
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ut_asserteq(4, map->range_count);
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map = syscon_get_regmap_by_driver_data(SYSCON_COUNT);
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ut_asserteq_ptr(ERR_PTR(-ENODEV), map);
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ut_asserteq(0x10, map_to_sysmem(syscon_get_first_range(SYSCON0)));
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ut_asserteq(0x20, map_to_sysmem(syscon_get_first_range(SYSCON1)));
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ut_asserteq_ptr(ERR_PTR(-ENODEV),
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syscon_get_first_range(SYSCON_COUNT));
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return 0;
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}
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DM_TEST(dm_test_regmap_syscon, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
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/* Read/Write/Modify test */
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static int dm_test_regmap_rw(struct unit_test_state *uts)
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{
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struct udevice *dev;
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struct regmap *map;
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uint reg;
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sandbox_set_enable_memio(true);
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ut_assertok(uclass_get_device(UCLASS_SYSCON, 0, &dev));
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map = syscon_get_regmap(dev);
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ut_assertok_ptr(map);
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ut_assertok(regmap_write(map, 0, 0xcacafafa));
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ut_assertok(regmap_write(map, 5, 0x55aa2211));
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ut_assertok(regmap_read(map, 0, ®));
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ut_asserteq(0xcacafafa, reg);
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ut_assertok(regmap_read(map, 5, ®));
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ut_asserteq(0x55aa2211, reg);
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ut_assertok(regmap_read(map, 0, ®));
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ut_asserteq(0xcacafafa, reg);
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ut_assertok(regmap_update_bits(map, 0, 0xff00ff00, 0x55aa2211));
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ut_assertok(regmap_read(map, 0, ®));
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ut_asserteq(0x55ca22fa, reg);
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ut_assertok(regmap_update_bits(map, 5, 0x00ff00ff, 0xcacafada));
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ut_assertok(regmap_read(map, 5, ®));
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ut_asserteq(0x55ca22da, reg);
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return 0;
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}
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DM_TEST(dm_test_regmap_rw, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
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/* Get/Set test */
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static int dm_test_regmap_getset(struct unit_test_state *uts)
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{
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struct udevice *dev;
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struct regmap *map;
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uint reg;
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struct layout {
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u32 val0;
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u32 val1;
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u32 val2;
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u32 val3;
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};
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sandbox_set_enable_memio(true);
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ut_assertok(uclass_get_device(UCLASS_SYSCON, 0, &dev));
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map = syscon_get_regmap(dev);
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ut_assertok_ptr(map);
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regmap_set(map, struct layout, val0, 0xcacafafa);
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regmap_set(map, struct layout, val3, 0x55aa2211);
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ut_assertok(regmap_get(map, struct layout, val0, ®));
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ut_asserteq(0xcacafafa, reg);
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ut_assertok(regmap_get(map, struct layout, val3, ®));
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ut_asserteq(0x55aa2211, reg);
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return 0;
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}
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DM_TEST(dm_test_regmap_getset, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
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/* Read polling test */
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static int dm_test_regmap_poll(struct unit_test_state *uts)
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{
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struct udevice *dev;
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struct regmap *map;
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uint reg;
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unsigned long start;
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ut_assertok(uclass_get_device(UCLASS_SYSCON, 0, &dev));
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map = syscon_get_regmap(dev);
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ut_assertok_ptr(map);
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start = get_timer(0);
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ut_assertok(regmap_write(map, 0, 0x0));
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ut_asserteq(-ETIMEDOUT,
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regmap_read_poll_timeout_test(map, 0, reg,
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(reg == 0xcacafafa),
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1, 5 * CONFIG_SYS_HZ,
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5 * CONFIG_SYS_HZ));
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ut_assert(get_timer(start) > (5 * CONFIG_SYS_HZ));
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return 0;
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}
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DM_TEST(dm_test_regmap_poll, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
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struct regmaptest_priv {
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struct regmap *cfg_regmap; /* For testing regmap_config options. */
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struct regmap *fld_regmap; /* For testing regmap fields. */
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struct regmap_field **fields;
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};
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static const struct reg_field field_cfgs[] = {
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{
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.reg = 0,
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.lsb = 0,
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.msb = 6,
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},
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{
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.reg = 2,
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.lsb = 4,
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.msb = 12,
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},
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{
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.reg = 2,
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.lsb = 12,
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.msb = 15,
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}
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};
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#define REGMAP_TEST_BUF_START 0
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#define REGMAP_TEST_BUF_SZ 5
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static int remaptest_probe(struct udevice *dev)
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{
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struct regmaptest_priv *priv = dev_get_priv(dev);
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struct regmap *regmap;
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struct regmap_field *field;
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struct regmap_config cfg;
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int i;
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static const int n = ARRAY_SIZE(field_cfgs);
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/*
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* To exercise all the regmap config options, create a regmap that
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* points to a custom memory area instead of the one defined in device
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* tree. Use 2-byte elements. To allow directly indexing into the
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* elements, use an offset shift of 1. So, accessing offset 1 gets the
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* element at index 1 at memory location 2.
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*
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* REGMAP_TEST_BUF_SZ is the number of elements, so we need to multiply
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* it by 2 because r_size expects number of bytes.
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*/
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cfg.reg_offset_shift = 1;
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cfg.r_start = REGMAP_TEST_BUF_START;
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cfg.r_size = REGMAP_TEST_BUF_SZ * 2;
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cfg.width = REGMAP_SIZE_16;
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regmap = devm_regmap_init(dev, NULL, NULL, &cfg);
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if (IS_ERR(regmap))
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return PTR_ERR(regmap);
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priv->cfg_regmap = regmap;
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memset(&cfg, 0, sizeof(struct regmap_config));
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cfg.width = REGMAP_SIZE_16;
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regmap = devm_regmap_init(dev, NULL, NULL, &cfg);
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if (IS_ERR(regmap))
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return PTR_ERR(regmap);
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priv->fld_regmap = regmap;
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priv->fields = devm_kzalloc(dev, sizeof(struct regmap_field *) * n,
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GFP_KERNEL);
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if (!priv->fields)
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return -ENOMEM;
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for (i = 0 ; i < n; i++) {
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field = devm_regmap_field_alloc(dev, priv->fld_regmap,
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field_cfgs[i]);
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if (IS_ERR(field))
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return PTR_ERR(field);
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priv->fields[i] = field;
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}
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return 0;
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}
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static const struct udevice_id regmaptest_ids[] = {
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{ .compatible = "sandbox,regmap_test" },
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{ }
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};
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U_BOOT_DRIVER(regmap_test) = {
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.name = "regmaptest_drv",
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.of_match = regmaptest_ids,
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.id = UCLASS_NOP,
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.probe = remaptest_probe,
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.priv_auto_alloc_size = sizeof(struct regmaptest_priv),
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};
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static int dm_test_devm_regmap(struct unit_test_state *uts)
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{
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int i = 0;
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u32 val;
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u16 pattern[REGMAP_TEST_BUF_SZ];
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u16 *buffer;
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struct udevice *dev;
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struct regmaptest_priv *priv;
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sandbox_set_enable_memio(true);
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/*
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* Map the memory area the regmap should point to so we can make sure
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* the writes actually go to that location.
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*/
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buffer = map_physmem(REGMAP_TEST_BUF_START,
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REGMAP_TEST_BUF_SZ * 2, MAP_NOCACHE);
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ut_assertok(uclass_get_device_by_name(UCLASS_NOP, "regmap-test_0",
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&dev));
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priv = dev_get_priv(dev);
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srand(get_ticks() + rand());
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for (i = 0; i < REGMAP_TEST_BUF_SZ; i++) {
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pattern[i] = rand();
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ut_assertok(regmap_write(priv->cfg_regmap, i, pattern[i]));
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}
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for (i = 0; i < REGMAP_TEST_BUF_SZ; i++) {
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ut_assertok(regmap_read(priv->cfg_regmap, i, &val));
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ut_asserteq(val, buffer[i]);
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ut_asserteq(val, pattern[i]);
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}
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ut_asserteq(-ERANGE, regmap_write(priv->cfg_regmap, REGMAP_TEST_BUF_SZ,
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val));
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ut_asserteq(-ERANGE, regmap_read(priv->cfg_regmap, REGMAP_TEST_BUF_SZ,
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&val));
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ut_asserteq(-ERANGE, regmap_write(priv->cfg_regmap, -1, val));
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ut_asserteq(-ERANGE, regmap_read(priv->cfg_regmap, -1, &val));
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return 0;
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}
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DM_TEST(dm_test_devm_regmap, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
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static int test_one_field(struct unit_test_state *uts,
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struct regmap *regmap,
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struct regmap_field *field,
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struct reg_field field_cfg)
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{
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int j;
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unsigned int val;
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int mask = (1 << (field_cfg.msb - field_cfg.lsb + 1)) - 1;
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int shift = field_cfg.lsb;
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ut_assertok(regmap_write(regmap, field_cfg.reg, 0));
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ut_assertok(regmap_read(regmap, field_cfg.reg, &val));
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ut_asserteq(0, val);
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for (j = 0; j <= mask; j++) {
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ut_assertok(regmap_field_write(field, j));
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ut_assertok(regmap_field_read(field, &val));
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ut_asserteq(j, val);
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ut_assertok(regmap_read(regmap, field_cfg.reg, &val));
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ut_asserteq(j << shift, val);
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}
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ut_assertok(regmap_field_write(field, mask + 1));
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ut_assertok(regmap_read(regmap, field_cfg.reg, &val));
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ut_asserteq(0, val);
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ut_assertok(regmap_field_write(field, 0xFFFF));
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ut_assertok(regmap_read(regmap, field_cfg.reg, &val));
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ut_asserteq(mask << shift, val);
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ut_assertok(regmap_write(regmap, field_cfg.reg, 0xFFFF));
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ut_assertok(regmap_field_write(field, 0));
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ut_assertok(regmap_read(regmap, field_cfg.reg, &val));
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ut_asserteq(0xFFFF & ~(mask << shift), val);
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return 0;
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}
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static int dm_test_devm_regmap_field(struct unit_test_state *uts)
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{
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int i, rc;
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struct udevice *dev;
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struct regmaptest_priv *priv;
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ut_assertok(uclass_get_device_by_name(UCLASS_NOP, "regmap-test_0",
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&dev));
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priv = dev_get_priv(dev);
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sandbox_set_enable_memio(true);
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for (i = 0 ; i < ARRAY_SIZE(field_cfgs); i++) {
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rc = test_one_field(uts, priv->fld_regmap, priv->fields[i],
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field_cfgs[i]);
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if (rc)
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break;
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}
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return 0;
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}
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DM_TEST(dm_test_devm_regmap_field, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
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