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e76cd5d4cf
There were a number of shared files that were using CONFIG_SYS_MPC85xx_DDR_ADDR, or CONFIG_SYS_MPC86xx_DDR_ADDR, and several variants (DDR2, DDR3). A recent patchset added 85xx-specific ones to code which was used by 86xx systems. After reviewing places where these constants were used, and noting that the type definitions of the pointers assigned to point to those addresses were the same, the cleanest approach to fixing this problem was to unify the namespace for the 85xx, 83xx, and 86xx DDR address definitions. This patch does: s/CONFIG_SYS_MPC8.xx_DDR/CONFIG_SYS_MPC8xxx_DDR/g All 85xx, 86xx, and 83xx have been built with this change. Signed-off-by: Andy Fleming <afleming@freescale.com> Tested-by: Andy Fleming <afleming@freescale.com> Acked-by: Kim Phillips <kim.phillips@freescale.com>
95 lines
2.8 KiB
C
95 lines
2.8 KiB
C
/*
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* Copyright 2008-2011 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* Version 2 as published by the Free Software Foundation.
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/processor.h>
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#include <asm/fsl_ddr_sdram.h>
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#if (CONFIG_CHIP_SELECTS_PER_CTRL > 4)
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#error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL
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#endif
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void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
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unsigned int ctrl_num)
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{
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unsigned int i;
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ccsr_ddr_t *ddr = (void *)CONFIG_SYS_MPC8xxx_DDR_ADDR;
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#if defined(CONFIG_SYS_FSL_ERRATUM_NMG_DDR120) && defined(CONFIG_MPC85xx)
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ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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uint svr;
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#endif
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if (ctrl_num) {
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printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num);
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return;
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}
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#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_DDR120
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/*
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* Set the DDR IO receiver to an acceptable bias point.
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* Fixed in Rev 2.1.
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*/
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svr = get_svr();
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if ((SVR_MAJ(svr) == 1) || IS_SVR_REV(svr, 2, 0)) {
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if ((regs->ddr_sdram_cfg & SDRAM_CFG_SDRAM_TYPE_MASK) ==
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SDRAM_CFG_SDRAM_TYPE_DDR2)
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out_be32(&gur->ddrioovcr, 0x90000000);
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else
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out_be32(&gur->ddrioovcr, 0xA8000000);
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}
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#endif
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for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
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if (i == 0) {
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out_be32(&ddr->cs0_bnds, regs->cs[i].bnds);
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out_be32(&ddr->cs0_config, regs->cs[i].config);
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} else if (i == 1) {
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out_be32(&ddr->cs1_bnds, regs->cs[i].bnds);
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out_be32(&ddr->cs1_config, regs->cs[i].config);
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} else if (i == 2) {
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out_be32(&ddr->cs2_bnds, regs->cs[i].bnds);
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out_be32(&ddr->cs2_config, regs->cs[i].config);
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} else if (i == 3) {
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out_be32(&ddr->cs3_bnds, regs->cs[i].bnds);
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out_be32(&ddr->cs3_config, regs->cs[i].config);
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}
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}
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out_be32(&ddr->timing_cfg_3, regs->timing_cfg_3);
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out_be32(&ddr->timing_cfg_0, regs->timing_cfg_0);
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out_be32(&ddr->timing_cfg_1, regs->timing_cfg_1);
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out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2);
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out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
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out_be32(&ddr->sdram_mode, regs->ddr_sdram_mode);
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out_be32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2);
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out_be32(&ddr->sdram_md_cntl, regs->ddr_sdram_md_cntl);
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out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval);
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out_be32(&ddr->sdram_data_init, regs->ddr_data_init);
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out_be32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl);
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out_be32(&ddr->init_addr, regs->ddr_init_addr);
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out_be32(&ddr->init_ext_addr, regs->ddr_init_ext_addr);
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/*
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* 200 painful micro-seconds must elapse between
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* the DDR clock setup and the DDR config enable.
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*/
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udelay(200);
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asm volatile("sync;isync");
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out_be32(&ddr->sdram_cfg, regs->ddr_sdram_cfg);
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/* Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done. */
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while (in_be32(&ddr->sdram_cfg_2) & 0x10) {
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udelay(10000); /* throttle polling rate */
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}
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}
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