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0e48dc5e41
As the PMECC hardware has different version. In SAMA5D4 chip, the PMECC ip can generate 0xff pmecc ECC value for all 0xff sector. According to this, add PMECC version check, if it's SAMA5D4 then we always let PMECC hardware to correct it. Signed-off-by: Josh Wu <josh.wu@atmel.com> Acked-by: Bo Shen <voice.shen@atmel.com> Acked-by: Andreas Bießmann <andreas.devel@googlemail.com>
173 lines
5.4 KiB
C
173 lines
5.4 KiB
C
/*
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* Error Corrected Code Controller (ECC) - System peripherals regsters.
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* Based on AT91SAM9260 datasheet revision B.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef ATMEL_NAND_ECC_H
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#define ATMEL_NAND_ECC_H
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#define ATMEL_ECC_CR 0x00 /* Control register */
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#define ATMEL_ECC_RST (1 << 0) /* Reset parity */
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#define ATMEL_ECC_MR 0x04 /* Mode register */
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#define ATMEL_ECC_PAGESIZE (3 << 0) /* Page Size */
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#define ATMEL_ECC_PAGESIZE_528 (0)
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#define ATMEL_ECC_PAGESIZE_1056 (1)
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#define ATMEL_ECC_PAGESIZE_2112 (2)
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#define ATMEL_ECC_PAGESIZE_4224 (3)
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#define ATMEL_ECC_SR 0x08 /* Status register */
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#define ATMEL_ECC_RECERR (1 << 0) /* Recoverable Error */
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#define ATMEL_ECC_ECCERR (1 << 1) /* ECC Single Bit Error */
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#define ATMEL_ECC_MULERR (1 << 2) /* Multiple Errors */
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#define ATMEL_ECC_PR 0x0c /* Parity register */
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#define ATMEL_ECC_BITADDR (0xf << 0) /* Bit Error Address */
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#define ATMEL_ECC_WORDADDR (0xfff << 4) /* Word Error Address */
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#define ATMEL_ECC_NPR 0x10 /* NParity register */
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#define ATMEL_ECC_NPARITY (0xffff << 0) /* NParity */
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/* Register access macros for PMECC */
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#define pmecc_readl(addr, reg) \
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readl(&addr->reg)
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#define pmecc_readb(addr, reg) \
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readb(&addr->reg)
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#define pmecc_writel(addr, reg, value) \
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writel((value), &addr->reg)
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/* PMECC Register Definitions */
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#define PMECC_MAX_SECTOR_NUM 8
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struct pmecc_regs {
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u32 cfg; /* 0x00 PMECC Configuration Register */
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u32 sarea; /* 0x04 PMECC Spare Area Size Register */
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u32 saddr; /* 0x08 PMECC Start Address Register */
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u32 eaddr; /* 0x0C PMECC End Address Register */
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u32 clk; /* 0x10 PMECC Clock Control Register */
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u32 ctrl; /* 0x14 PMECC Control Register */
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u32 sr; /* 0x18 PMECC Status Register */
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u32 ier; /* 0x1C PMECC Interrupt Enable Register */
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u32 idr; /* 0x20 PMECC Interrupt Disable Register */
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u32 imr; /* 0x24 PMECC Interrupt Mask Register */
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u32 isr; /* 0x28 PMECC Interrupt Status Register */
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u32 reserved0[5]; /* 0x2C-0x3C Reserved */
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/* 0x40 + sector_num * (0x40), Redundancy Registers */
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struct {
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u8 ecc[44]; /* PMECC Generated Redundancy Byte Per Sector */
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u32 reserved1[5];
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} ecc_port[PMECC_MAX_SECTOR_NUM];
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/* 0x240 + sector_num * (0x40) Remainder Registers */
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struct {
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u32 rem[12];
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u32 reserved2[4];
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} rem_port[PMECC_MAX_SECTOR_NUM];
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u32 reserved3[16]; /* 0x440-0x47C Reserved */
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};
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/* For PMECC Configuration Register */
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#define PMECC_CFG_BCH_ERR2 (0 << 0)
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#define PMECC_CFG_BCH_ERR4 (1 << 0)
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#define PMECC_CFG_BCH_ERR8 (2 << 0)
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#define PMECC_CFG_BCH_ERR12 (3 << 0)
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#define PMECC_CFG_BCH_ERR24 (4 << 0)
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#define PMECC_CFG_SECTOR512 (0 << 4)
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#define PMECC_CFG_SECTOR1024 (1 << 4)
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#define PMECC_CFG_PAGE_1SECTOR (0 << 8)
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#define PMECC_CFG_PAGE_2SECTORS (1 << 8)
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#define PMECC_CFG_PAGE_4SECTORS (2 << 8)
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#define PMECC_CFG_PAGE_8SECTORS (3 << 8)
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#define PMECC_CFG_READ_OP (0 << 12)
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#define PMECC_CFG_WRITE_OP (1 << 12)
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#define PMECC_CFG_SPARE_ENABLE (1 << 16)
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#define PMECC_CFG_SPARE_DISABLE (0 << 16)
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#define PMECC_CFG_AUTO_ENABLE (1 << 20)
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#define PMECC_CFG_AUTO_DISABLE (0 << 20)
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/* For PMECC Clock Control Register */
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#define PMECC_CLK_133MHZ (2 << 0)
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/* For PMECC Control Register */
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#define PMECC_CTRL_RST (1 << 0)
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#define PMECC_CTRL_DATA (1 << 1)
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#define PMECC_CTRL_USER (1 << 2)
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#define PMECC_CTRL_ENABLE (1 << 4)
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#define PMECC_CTRL_DISABLE (1 << 5)
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/* For PMECC Status Register */
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#define PMECC_SR_BUSY (1 << 0)
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#define PMECC_SR_ENABLE (1 << 4)
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/* PMERRLOC Register Definitions */
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struct pmecc_errloc_regs {
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u32 elcfg; /* 0x00 Error Location Configuration Register */
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u32 elprim; /* 0x04 Error Location Primitive Register */
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u32 elen; /* 0x08 Error Location Enable Register */
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u32 eldis; /* 0x0C Error Location Disable Register */
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u32 elsr; /* 0x10 Error Location Status Register */
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u32 elier; /* 0x14 Error Location Interrupt Enable Register */
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u32 elidr; /* 0x08 Error Location Interrupt Disable Register */
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u32 elimr; /* 0x0C Error Location Interrupt Mask Register */
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u32 elisr; /* 0x20 Error Location Interrupt Status Register */
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u32 reserved0; /* 0x24 Reserved */
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u32 sigma[25]; /* 0x28-0x88 Error Location Sigma Registers */
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u32 el[24]; /* 0x8C-0xE8 Error Location Registers */
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u32 reserved1[5]; /* 0xEC-0xFC Reserved */
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/*
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* 0x100-0x1F8:
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* Reserved for AT91SAM9X5, AT91SAM9N12.
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* HSMC registers for SAMA5D3, SAMA5D4.
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*/
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u32 reserved2[63];
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/*
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* 0x1FC:
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* PMECC version for AT91SAM9X5, AT91SAM9N12.
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* HSMC version for SAMA5D3, SAMA5D4. Can refer as PMECC version.
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*/
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u32 version;
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};
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/* For Error Location Configuration Register */
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#define PMERRLOC_ELCFG_SECTOR_512 (0 << 0)
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#define PMERRLOC_ELCFG_SECTOR_1024 (1 << 0)
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#define PMERRLOC_ELCFG_NUM_ERRORS(n) ((n) << 16)
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/* For Error Location Disable Register */
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#define PMERRLOC_DISABLE (1 << 0)
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/* For Error Location Interrupt Status Register */
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#define PMERRLOC_ERR_NUM_MASK (0x1f << 8)
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#define PMERRLOC_CALC_DONE (1 << 0)
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/* PMECC IP version */
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#define PMECC_VERSION_SAMA5D4 0x113
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#define PMECC_VERSION_SAMA5D3 0x112
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#define PMECC_VERSION_AT91SAM9N12 0x102
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#define PMECC_VERSION_AT91SAM9X5 0x101
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/* Galois field dimension */
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#define PMECC_GF_DIMENSION_13 13
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#define PMECC_GF_DIMENSION_14 14
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/* Primitive Polynomial used by PMECC */
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#define PMECC_GF_13_PRIMITIVE_POLY 0x201b
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#define PMECC_GF_14_PRIMITIVE_POLY 0x4443
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#define PMECC_INDEX_TABLE_SIZE_512 0x2000
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#define PMECC_INDEX_TABLE_SIZE_1024 0x4000
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#define PMECC_MAX_TIMEOUT_US (100 * 1000)
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#endif
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