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97405d843e
Update PLL values. SYS_CLKSEL value for 20MHz is changed to 2. In other platforms SYS_CLKSEL value 2 represents reserved. But in sys_clk array ind 1 is used for 13Mhz. Since other platforms are not using 13Mhz, reusing index 1 for 20MHz. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Sricharan R <r.sricharan@ti.com> |
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.. | ||
clock.h | ||
cpu.h | ||
ehci.h | ||
gpio.h | ||
i2c.h | ||
mmc_host_def.h | ||
mux_omap4.h | ||
omap.h | ||
spl.h | ||
sys_proto.h |