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https://github.com/AsahiLinux/u-boot
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95b602bab5
The latest PPC4xx register cleanup patch missed some SDRAM defines. This patch now changes lower case UIC defines to upper case. Also some names are changed to match the naming in the IBM/AMCC users manuals (e.g. mem_mcopt1 -> SDRAM0_CFG). Signed-off-by: Stefan Roese <sr@denx.de>
280 lines
7.6 KiB
C
280 lines
7.6 KiB
C
/*
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* (C) Copyright 2001
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* Erik Theisen, Wave 7 Optics, etheisen@mindspring.com.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <command.h>
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#include "w7o.h"
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#include <asm/processor.h>
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#include "vpd.h"
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#include "errors.h"
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#include <watchdog.h>
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unsigned long get_dram_size (void);
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void sdram_init(void);
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/*
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* Macros to transform values
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* into environment strings.
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*/
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#define XMK_STR(x) #x
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#define MK_STR(x) XMK_STR(x)
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/* ------------------------------------------------------------------------- */
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int board_early_init_f (void)
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{
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#if defined(CONFIG_W7OLMG)
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/*
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* Setup GPIO pins - reset devices.
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*/
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out32 (PPC405GP_GPIO0_ODR, 0x10000000); /* one open drain pin */
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out32 (PPC405GP_GPIO0_OR, 0x3E000000); /* set output pins to default */
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out32 (PPC405GP_GPIO0_TCR, 0x7f800000); /* setup for output */
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/*
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* IRQ 0-15 405GP internally generated; active high; level sensitive
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* IRQ 16 405GP internally generated; active low; level sensitive
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* IRQ 17-24 RESERVED
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* IRQ 25 (EXT IRQ 0) XILINX; active low; level sensitive
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* IRQ 26 (EXT IRQ 1) PCI INT A; active low; level sensitive
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* IRQ 27 (EXT IRQ 2) PCI INT B; active low; level sensitive
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* IRQ 28 (EXT IRQ 3) SAM 2; active low; level sensitive
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* IRQ 29 (EXT IRQ 4) Battery Bad; active low; level sensitive
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* IRQ 30 (EXT IRQ 5) Level One PHY; active low; level sensitive
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* IRQ 31 (EXT IRQ 6) SAM 1; active high; level sensitive
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*/
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mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
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mtdcr (UIC0ER, 0x00000000); /* disable all ints */
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mtdcr (UIC0CR, 0x00000000); /* set all to be non-critical */
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mtdcr (UIC0PR, 0xFFFFFF80); /* set int polarities */
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mtdcr (UIC0TR, 0x10000000); /* set int trigger levels */
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mtdcr (UIC0VCR, 0x00000001); /* set vect base=0,
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INT0 highest priority */
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mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
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#elif defined(CONFIG_W7OLMC)
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/*
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* Setup GPIO pins
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*/
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out32 (PPC405GP_GPIO0_ODR, 0x01800000); /* XCV Done Open Drain */
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out32 (PPC405GP_GPIO0_OR, 0x03800000); /* set out pins to default */
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out32 (PPC405GP_GPIO0_TCR, 0x66C00000); /* setup for output */
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/*
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* IRQ 0-15 405GP internally generated; active high; level sensitive
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* IRQ 16 405GP internally generated; active low; level sensitive
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* IRQ 17-24 RESERVED
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* IRQ 25 (EXT IRQ 0) DBE 0; active low; level sensitive
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* IRQ 26 (EXT IRQ 1) DBE 1; active low; level sensitive
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* IRQ 27 (EXT IRQ 2) DBE 2; active low; level sensitive
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* IRQ 28 (EXT IRQ 3) DBE Common; active low; level sensitive
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* IRQ 29 (EXT IRQ 4) PCI; active low; level sensitive
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* IRQ 30 (EXT IRQ 5) RCMM Reset; active low; level sensitive
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* IRQ 31 (EXT IRQ 6) PHY; active high; level sensitive
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*/
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mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
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mtdcr (UIC0ER, 0x00000000); /* disable all ints */
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mtdcr (UIC0CR, 0x00000000); /* set all to be non-critical */
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mtdcr (UIC0PR, 0xFFFFFF80); /* set int polarities */
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mtdcr (UIC0TR, 0x10000000); /* set int trigger levels */
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mtdcr (UIC0VCR, 0x00000001); /* set vect base=0,
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INT0 highest priority */
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mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
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#else /* Unknown */
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# error "Unknown W7O board configuration"
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#endif
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WATCHDOG_RESET (); /* Reset the watchdog */
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temp_uart_init (); /* init the uart for debug */
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WATCHDOG_RESET (); /* Reset the watchdog */
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test_led (); /* test the LEDs */
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test_sdram (get_dram_size ()); /* test the dram */
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log_stat (ERR_POST1); /* log status,post1 complete */
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return 0;
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}
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/* ------------------------------------------------------------------------- */
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/*
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* Check Board Identity:
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*/
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int checkboard (void)
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{
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VPD vpd;
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puts ("Board: ");
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/* VPD data present in I2C EEPROM */
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if (vpd_get_data (CONFIG_SYS_DEF_EEPROM_ADDR, &vpd) == 0) {
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/*
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* Known board type.
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*/
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if (vpd.productId[0] &&
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((strncmp (vpd.productId, "GMM", 3) == 0) ||
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(strncmp (vpd.productId, "CMM", 3) == 0))) {
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/* Output board information on startup */
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printf ("\"%s\", revision '%c', serial# %ld, manufacturer %u\n", vpd.productId, vpd.revisionId, vpd.serialNum, vpd.manuID);
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return (0);
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}
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}
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puts ("### Unknown HW ID - assuming NOTHING\n");
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return (0);
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}
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/* ------------------------------------------------------------------------- */
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phys_size_t initdram (int board_type)
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{
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/*
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* ToDo: Move the asm init routine sdram_init() to this C file,
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* or even better use some common ppc4xx code available
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* in cpu/ppc4xx
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*/
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sdram_init();
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return get_dram_size ();
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}
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unsigned long get_dram_size (void)
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{
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int tmp, i, regs[4];
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int size = 0;
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/* Get bank Size registers */
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mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR); /* get bank 0 config reg */
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regs[0] = mfdcr (SDRAM0_CFGDATA);
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mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR); /* get bank 1 config reg */
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regs[1] = mfdcr (SDRAM0_CFGDATA);
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mtdcr (SDRAM0_CFGADDR, SDRAM0_B2CR); /* get bank 2 config reg */
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regs[2] = mfdcr (SDRAM0_CFGDATA);
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mtdcr (SDRAM0_CFGADDR, SDRAM0_B3CR); /* get bank 3 config reg */
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regs[3] = mfdcr (SDRAM0_CFGDATA);
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/* compute the size, add each bank if enabled */
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for (i = 0; i < 4; i++) {
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if (regs[i] & 0x0001) { /* if enabled, */
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tmp = ((regs[i] >> (31 - 14)) & 0x7); /* get size bits */
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tmp = 0x400000 << tmp; /* Size bits X 4MB = size */
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size += tmp;
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}
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}
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return size;
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}
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int misc_init_f (void)
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{
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return 0;
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}
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static void w7o_env_init (VPD * vpd)
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{
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/*
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* Read VPD
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*/
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if (vpd_get_data (CONFIG_SYS_DEF_EEPROM_ADDR, vpd) != 0)
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return;
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/*
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* Known board type.
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*/
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if (vpd->productId[0] &&
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((strncmp (vpd->productId, "GMM", 3) == 0) ||
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(strncmp (vpd->productId, "CMM", 3) == 0))) {
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char buf[30];
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char *eth;
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char *serial = getenv ("serial#");
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char *ethaddr = getenv ("ethaddr");
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/* Set 'serial#' envvar if serial# isn't set */
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if (!serial) {
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sprintf (buf, "%s-%ld", vpd->productId,
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vpd->serialNum);
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setenv ("serial#", buf);
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}
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/* Set 'ethaddr' envvar if 'ethaddr' envvar is the default */
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eth = (char *)(vpd->ethAddrs[0]);
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if (ethaddr
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&& (strcmp (ethaddr, MK_STR (CONFIG_ETHADDR)) == 0)) {
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/* Now setup ethaddr */
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sprintf (buf, "%02x:%02x:%02x:%02x:%02x:%02x",
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eth[0], eth[1], eth[2], eth[3], eth[4],
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eth[5]);
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setenv ("ethaddr", buf);
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}
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}
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} /* w7o_env_init() */
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int misc_init_r (void)
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{
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VPD vpd; /* VPD information */
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#if defined(CONFIG_W7OLMG)
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unsigned long greg; /* GPIO Register */
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greg = in32 (PPC405GP_GPIO0_OR);
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/*
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* XXX - Unreset devices - this should be moved into VxWorks driver code
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*/
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greg |= 0x41800000L; /* SAM, PHY, Galileo */
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out32 (PPC405GP_GPIO0_OR, greg); /* set output pins to default */
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#endif /* CONFIG_W7OLMG */
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/*
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* Initialize W7O environment variables
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*/
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w7o_env_init (&vpd);
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/*
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* Initialize the FPGA(s).
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*/
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if (init_fpga () == 0)
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test_fpga ((unsigned short *) CONFIG_FPGAS_BASE);
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/* More POST testing. */
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post2 ();
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/* Done with hardware initialization and POST. */
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log_stat (ERR_POSTOK);
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/* Call silly, fail safe boot init routine */
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init_fsboot ();
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return (0);
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}
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