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On K3 systems U-Boot runs on both an R5 and a large ARM cores (usually A53 or A72). The large ARMs are coherent with the DMA controllers and the SYSFW that perform authentication. And previously the R5 core did not enable caches. Now that R5 does enable caching we need to be sure to clean out any of the image that may still only be in cache before we read it using external DMA for authentication. Although not expected to happen, it may be possible that the data was read back into cache after the flush but before the external operation, in this case we must invalidate our stale local cached version. Signed-off-by: Andrew F. Davis <afd@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> |
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