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The T4240QDS is a high-performance computing evaluation, development and test platform supporting the T4240 QorIQ Power Architecture™ processor. SERDES Connections 32 lanes grouped into four 8-lane banks Two “front side” banks dedicated to Ethernet Two “back side” banks dedicated to other protocols DDR Controllers Three independant 64-bit DDR3 controllers Supports rates up to 2133 MHz data-rate Supports two DDR3/DDR3LP UDIMM/RDIMMs per controller QIXIS System Logic FPGA Each DDR controller has two DIMM slots. The first slot of each controller has up to 4 chip selects to support single-, dual- and quad-rank DIMMs. The second slot has only 2 chip selects to support single- and dual-rank DIMMs. At any given time, up to total 4 chip selects can be used. Detail information can be found in doc/README.t4qds Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
56 lines
1.7 KiB
C
56 lines
1.7 KiB
C
/*
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* Copyright 2012 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __T4020QDS_QIXIS_H__
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#define __T4020QDS_QIXIS_H__
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/* Definitions of QIXIS Registers for T4020QDS */
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/* BRDCFG4[4:7]] select EC1 and EC2 as a pair */
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#define BRDCFG4_EMISEL_MASK 0xE0
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#define BRDCFG4_EMISEL_SHIFT 5
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/* SYSCLK */
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#define QIXIS_SYSCLK_66 0x0
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#define QIXIS_SYSCLK_83 0x1
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#define QIXIS_SYSCLK_100 0x2
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#define QIXIS_SYSCLK_125 0x3
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#define QIXIS_SYSCLK_133 0x4
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#define QIXIS_SYSCLK_150 0x5
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#define QIXIS_SYSCLK_160 0x6
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#define QIXIS_SYSCLK_166 0x7
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/* DDRCLK */
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#define QIXIS_DDRCLK_66 0x0
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#define QIXIS_DDRCLK_100 0x1
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#define QIXIS_DDRCLK_125 0x2
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#define QIXIS_DDRCLK_133 0x3
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#define BRDCFG5_RESET 0x00
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#define BRDCFG12_SD3EN_MASK 0x20
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#define BRDCFG12_SD3MX_MASK 0x08
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#define BRDCFG12_SD3MX_SLOT5 0x08
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#define BRDCFG12_SD3MX_SLOT6 0x00
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#define BRDCFG12_SD4EN_MASK 0x04
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#define BRDCFG12_SD4MX_MASK 0x03
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#define BRDCFG12_SD4MX_SLOT7 0x02
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#define BRDCFG12_SD4MX_SLOT8 0x01
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#define BRDCFG12_SD4MX_AURO_SATA 0x00
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#endif
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