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68c7c008e8
In order to maintain compatibility with the Linux DTS, the entire fsl-mc node is added but instead of being probed by a dedicated bus driver it will be a simple-mfd. Also, annotate the external MDIO nodes and describe the PHYs (8 x VSC8514, AQR105). Also, add phy-handles for the dpmacs to their associated PHY. Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
168 lines
2.5 KiB
Text
168 lines
2.5 KiB
Text
// SPDX-License-Identifier: GPL-2.0+ OR X11
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/*
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* NXP ls1088a RDB board device tree source
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*
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* Copyright 2017 NXP
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*/
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/dts-v1/;
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#include "fsl-ls1088a.dtsi"
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/ {
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model = "NXP Layerscape 1088a RDB Board";
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compatible = "fsl,ls1088a-rdb", "fsl,ls1088a";
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aliases {
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spi0 = &qspi;
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};
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};
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&dpmac1 {
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status = "okay";
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phy-connection-type = "xgmii";
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};
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&dpmac2 {
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status = "okay";
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phy-handle = <&mdio2_phy1>;
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phy-connection-type = "xgmii";
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};
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&dpmac3 {
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status = "okay";
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phy-handle = <&mdio1_phy5>;
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phy-connection-type = "qsgmii";
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};
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&dpmac4 {
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status = "okay";
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phy-handle = <&mdio1_phy6>;
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phy-connection-type = "qsgmii";
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};
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&dpmac5 {
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status = "okay";
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phy-handle = <&mdio1_phy7>;
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phy-connection-type = "qsgmii";
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};
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&dpmac6 {
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status = "okay";
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phy-handle = <&mdio1_phy8>;
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phy-connection-type = "qsgmii";
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};
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&dpmac7 {
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status = "okay";
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phy-handle = <&mdio1_phy1>;
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phy-connection-type = "qsgmii";
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};
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&dpmac8 {
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status = "okay";
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phy-handle = <&mdio1_phy2>;
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phy-connection-type = "qsgmii";
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};
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&dpmac9 {
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status = "okay";
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phy-handle = <&mdio1_phy3>;
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phy-connection-type = "qsgmii";
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};
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&dpmac10 {
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status = "okay";
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phy-handle = <&mdio1_phy4>;
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phy-connection-type = "qsgmii";
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};
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&emdio1 {
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status = "okay";
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/* Freescale F104 PHY1 */
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mdio1_phy1: emdio1_phy@1 {
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reg = <0x1c>;
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};
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mdio1_phy2: emdio1_phy@2 {
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reg = <0x1d>;
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};
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mdio1_phy3: emdio1_phy@3 {
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reg = <0x1e>;
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};
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mdio1_phy4: emdio1_phy@4 {
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reg = <0x1f>;
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};
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/* F104 PHY2 */
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mdio1_phy5: emdio1_phy@5 {
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reg = <0x0c>;
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};
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mdio1_phy6: emdio1_phy@6 {
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reg = <0x0d>;
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};
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mdio1_phy7: emdio1_phy@7 {
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reg = <0x0e>;
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};
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mdio1_phy8: emdio1_phy@8 {
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reg = <0x0f>;
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};
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};
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&emdio2 {
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status = "okay";
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/* Aquantia AQR105 10G PHY */
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mdio2_phy1: emdio2_phy@1 {
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compatible = "ethernet-phy-ieee802.3-c45";
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interrupts = <0 2 0x4>;
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reg = <0x0>;
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};
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};
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&i2c0 {
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status = "okay";
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u-boot,dm-pre-reloc;
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i2c-mux@77 {
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compatible = "nxp,pca9547";
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reg = <0x77>;
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#address-cells = <1>;
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#size-cells = <0>;
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i2c@3 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x3>;
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rtc@51 {
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compatible = "pcf2127-rtc";
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reg = <0x51>;
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};
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};
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};
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};
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&qspi {
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bus-num = <0>;
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status = "okay";
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qflash0: s25fs512s@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "jedec,spi-nor";
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spi-max-frequency = <50000000>;
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reg = <0>;
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};
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qflash1: s25fs512s@1 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "jedec,spi-nor";
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spi-max-frequency = <50000000>;
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reg = <1>;
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};
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};
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&sata {
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status = "okay";
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};
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