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d3ee9dbd59
Per NXP requirement, we rename all the NXP EdgeLock Secure Enclave code including comment, folder and API name to ELE to align. Signed-off-by: Peng Fan <peng.fan@nxp.com>
266 lines
6.5 KiB
C
266 lines
6.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright 2022 NXP
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*/
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#ifndef __ASM_ARCH_IMX9_CCM_REGS_H__
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#define __ASM_ARCH_IMX9_CCM_REGS_H__
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#define IMX93_CLK_ROOT_MAX 95
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#define IMX93_CLK_CCGR_MAX 127
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#define ARM_A55_PERIPH_CLK_ROOT 0
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#define ARM_A55_MTR_BUS_CLK_ROOT 1
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#define ARM_A55_CLK_ROOT 2
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#define M33_CLK_ROOT 3
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#define ELE_CLK_ROOT 4
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#define BUS_WAKEUP_CLK_ROOT 5
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#define BUS_AON_CLK_ROOT 6
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#define WAKEUP_AXI_CLK_ROOT 7
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#define SWO_TRACE_CLK_ROOT 8
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#define M33_SYSTICK_CLK_ROOT 9
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#define FLEXIO1_CLK_ROOT 10
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#define FLEXIO2_CLK_ROOT 11
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#define LPIT1_CLK_ROOT 12
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#define LPIT2_CLK_ROOT 13
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#define LPTMR1_CLK_ROOT 14
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#define LPTMR2_CLK_ROOT 15
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#define TPM1_CLK_ROOT 16
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#define TPM2_CLK_ROOT 17
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#define TPM3_CLK_ROOT 18
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#define TPM4_CLK_ROOT 19
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#define TPM5_CLK_ROOT 20
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#define TPM6_CLK_ROOT 21
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#define FLEXSPI1_CLK_ROOT 22
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#define CAN1_CLK_ROOT 23
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#define CAN2_CLK_ROOT 24
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#define LPUART1_CLK_ROOT 25
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#define LPUART2_CLK_ROOT 26
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#define LPUART3_CLK_ROOT 27
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#define LPUART4_CLK_ROOT 28
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#define LPUART5_CLK_ROOT 29
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#define LPUART6_CLK_ROOT 30
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#define LPUART7_CLK_ROOT 31
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#define LPUART8_CLK_ROOT 32
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#define LPI2C1_CLK_ROOT 33
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#define LPI2C2_CLK_ROOT 34
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#define LPI2C3_CLK_ROOT 35
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#define LPI2C4_CLK_ROOT 36
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#define LPI2C5_CLK_ROOT 37
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#define LPI2C6_CLK_ROOT 38
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#define LPI2C7_CLK_ROOT 39
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#define LPI2C8_CLK_ROOT 40
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#define LPSPI1_CLK_ROOT 41
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#define LPSPI2_CLK_ROOT 42
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#define LPSPI3_CLK_ROOT 43
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#define LPSPI4_CLK_ROOT 44
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#define LPSPI5_CLK_ROOT 45
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#define LPSPI6_CLK_ROOT 46
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#define LPSPI7_CLK_ROOT 47
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#define LPSPI8_CLK_ROOT 48
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#define I3C1_CLK_ROOT 49
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#define I3C2_CLK_ROOT 50
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#define USDHC1_CLK_ROOT 51
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#define USDHC2_CLK_ROOT 52
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#define USDHC3_CLK_ROOT 53
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#define SAI1_CLK_ROOT 54
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#define SAI2_CLK_ROOT 55
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#define SAI3_CLK_ROOT 56
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#define CCM_CKO1_CLK_ROOT 57
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#define CCM_CKO2_CLK_ROOT 58
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#define CCM_CKO3_CLK_ROOT 59
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#define CCM_CKO4_CLK_ROOT 60
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#define HSIO_CLK_ROOT 61
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#define HSIO_USB_TEST_60M_CLK_ROOT 62
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#define HSIO_ACSCAN_80M_CLK_ROOT 63
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#define HSIO_ACSCAN_480M_CLK_ROOT 64
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#define NIC_CLK_ROOT 65
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#define NIC_APB_CLK_ROOT 66
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#define ML_APB_CLK_ROOT 67
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#define ML_CLK_ROOT 68
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#define MEDIA_AXI_CLK_ROOT 69
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#define MEDIA_APB_CLK_ROOT 70
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#define MEDIA_LDB_CLK_ROOT 71
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#define MEDIA_DISP_PIX_CLK_ROOT 72
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#define CAM_PIX_CLK_ROOT 73
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#define MIPI_TEST_BYTE_CLK_ROOT 74
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#define MIPI_PHY_CFG_CLK_ROOT 75
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#define DRAM_ALT_CLK_ROOT 76
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#define DRAM_APB_CLK_ROOT 77
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#define ADC_CLK_ROOT 78
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#define PDM_CLK_ROOT 79
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#define TSTMR1_CLK_ROOT 80
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#define TSTMR2_CLK_ROOT 81
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#define MQS1_CLK_ROOT 82
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#define MQS2_CLK_ROOT 83
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#define AUDIO_XCVR_CLK_ROOT 84
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#define SPDIF_CLK_ROOT 85
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#define ENET_CLK_ROOT 86
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#define ENET_TIMER1_CLK_ROOT 87
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#define ENET_TIMER2_CLK_ROOT 88
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#define ENET_REF_CLK_ROOT 89
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#define ENET_REF_PHY_CLK_ROOT 90
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#define I3C1_SLOW_CLK_ROOT 91
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#define I3C2_SLOW_CLK_ROOT 92
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#define USB_PHY_BURUNIN_CLK_ROOT 93
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#define PAL_CAME_SCAN_CLK_ROOT 94
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#define CLK_ROOT_NUM 95
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#define CCGR_A55 0
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#define CCGR_CM33 1
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#define CCGR_ARMTROUT 2
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#define CCGR_SENT 3
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#define CCGR_BUSM 4
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#define CCGR_BUS7 5
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#define CCGR_BUSD 6
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#define CCGR_ANAD 7
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#define CCGR_SRC 8
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#define CCGR_CCM 9
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#define CCGR_GPC 10
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#define CCGR_ADC 11
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#define CCGR_WDG1 12
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#define CCGR_WDG2 13
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#define CCGR_WDG3 14
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#define CCGR_WDG4 15
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#define CCGR_WDG5 16
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#define CCGR_SEM1 17
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#define CCGR_SEM2 18
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#define CCGR_MUA 19
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#define CCGR_MUB 20
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#define CCGR_DMA1 21
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#define CCGR_DMA2 22
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#define CCGR_ROMCA55 23
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#define CCGR_ROMCM33 24
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#define CCGR_QSP1 25
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#define CCGR_AONRDC 26
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#define CCGR_WKUPRDC 27
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#define CCGR_FUSE 28
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#define CCGR_SNVH 29
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#define CCGR_SNVS 30
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#define CCGR_TRAC 31
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#define CCGR_SWO 32
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#define CCGR_IOCG 33
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#define CCGR_PIO1 34
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#define CCGR_PIO2 35
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#define CCGR_PIO3 36
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#define CCGR_PIO4 37
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#define CCGR_FIO1 38
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#define CCGR_FIO2 39
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#define CCGR_PIT1 40
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#define CCGR_PIT2 41
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#define CCGR_GPT1 42
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#define CCGR_GPT2 43
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#define CCGR_TPM1 44
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#define CCGR_TPM2 45
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#define CCGR_TPM3 46
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#define CCGR_TPM4 47
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#define CCGR_TPM5 48
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#define CCGR_TPM6 49
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#define CCGR_CAN1 50
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#define CCGR_CAN2 51
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#define CCGR_URT1 52
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#define CCGR_URT2 53
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#define CCGR_URT3 54
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#define CCGR_URT4 55
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#define CCGR_URT5 56
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#define CCGR_URT6 57
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#define CCGR_URT7 58
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#define CCGR_URT8 59
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#define CCGR_I2C1 60
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#define CCGR_I2C2 61
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#define CCGR_I2C3 62
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#define CCGR_I2C4 63
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#define CCGR_I2C5 64
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#define CCGR_I2C6 65
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#define CCGR_I2C7 66
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#define CCGR_I2C8 67
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#define CCGR_SPI1 68
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#define CCGR_SPI2 69
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#define CCGR_SPI3 70
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#define CCGR_SPI4 71
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#define CCGR_SPI5 72
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#define CCGR_SPI6 73
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#define CCGR_SPI7 74
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#define CCGR_SPI8 75
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#define CCGR_I3C1 76
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#define CCGR_I3C2 77
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#define CCGR_USDHC1 78
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#define CCGR_USDHC2 79
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#define CCGR_USDHC3 80
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#define CCGR_SAI1 81
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#define CCGR_SAI2 82
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#define CCGR_SAI3 83
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#define CCGR_W2AO 84
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#define CCGR_AO2W 85
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#define CCGR_MIPIC 86
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#define CCGR_MIPID 87
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#define CCGR_LVDS 88
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#define CCGR_LCDIF 89
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#define CCGR_PXP 90
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#define CCGR_ISI 91
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#define CCGR_NMED 92
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#define CCGR_DFI 93
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#define CCGR_DDRC 94
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#define CCGR_DFIC 95
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#define CCGR_DSSI 96
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#define CCGR_DBYP 97
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#define CCGR_DAPB 98
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#define CCGR_DRAMP 99
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#define CCGR_DCLKC 100
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#define CCGR_NCTL 101
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#define CCGR_GIC 102
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#define CCGR_NICAPB 103
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#define CCGR_USBC 104
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#define CCGR_USBT 105
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#define CCGR_HSIO 106
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#define CCGR_PDM 107
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#define CCGR_MQS1 108
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#define CCGR_MQS2 109
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#define CCGR_AXCVR 110
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#define CCGR_MECC 111
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#define CCGR_SPDIF 112
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#define CCGR_ML2NIC 113
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#define CCGR_MED2NIC 114
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#define CCGR_HSIO2NIC 115
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#define CCGR_W2NIC 116
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#define CCGR_NIC2W 117
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#define CCGR_NIC2DDR 118
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#define CCGR_HSIO32K 119
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#define CCGR_ENET1 120
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#define CCGR_ENETQOS 121
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#define CCGR_SYSCNT 122
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#define CCGR_TSTMR1 123
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#define CCGR_TSTMR2 124
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#define CCGR_TMC 125
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#define CCGR_PMRO 126
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#define CCGR_NUM 127
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#define SHARED_GPR_EXT_CLK 0
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#define SHARED_GPR_EXT_CLK_SEL_EXT1 0
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#define SHARED_GPR_EXT_CLK_SEL_EXT2 BIT(0)
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#define SHARED_GPR_EXT_CLK_SEL_EXT3 BIT(1)
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#define SHARED_GPR_EXT_CLK_SEL_EXT4 GENMASK(1, 0)
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#define SHARED_GPR_A55_CLK 1
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#define SHARED_GPR_A55_CLK_SEL_CCM 0
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#define SHARED_GPR_A55_CLK_SEL_PLL BIT(0)
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#define SHARED_GPR_DRAM_CLK 2
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#define SHARED_GPR_DRAM_CLK_SEL_PLL 0
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#define SHARED_GPR_DRAM_CLK_SEL_CCM BIT(0)
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#define SHARED_GPR_NUM 8
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#define PRIVATE_GPR_NUM 8
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#define CLK_ROOT_STATUS_OFF BIT(24)
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#define CLK_ROOT_STATUS_CHANGING BIT(31)
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#define CLK_ROOT_MUX_MASK GENMASK(9, 8)
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#define CLK_ROOT_MUX_SHIFT 8
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#define CLK_ROOT_DIV_MASK GENMASK(7, 0)
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#define CCM_AUTHEN_LOCK_TZ BIT(11)
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#define CCM_AUTHEN_TZ_NS BIT(9)
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#define CCM_AUTHEN_TZ_USER BIT(8)
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#define CCM_AUTHEN_CPULPM_MODE BIT(2)
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#define CCM_AUTHEN_AUTO_CTRL BIT(3)
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#endif
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