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94d77fb656
Locking sequence for all the dplls is same. In the current code same sequence is done repeatedly for each dpll. Instead have a generic function for locking dplls and pass dpll data to that function. This is derived from OMAP4 boards. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Tested-by: Heiko Schocher <hs@denx.de> Acked-by: Heiko Schocher <hs@denx.de>
304 lines
9.2 KiB
C
304 lines
9.2 KiB
C
/*
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* ddr_defs.h
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*
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* ddr specific header
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*
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* Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _DDR_DEFS_H
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#define _DDR_DEFS_H
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#include <asm/arch/hardware.h>
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#include <asm/emif.h>
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/* AM335X EMIF Register values */
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#define VTP_CTRL_READY (0x1 << 5)
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#define VTP_CTRL_ENABLE (0x1 << 6)
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#define VTP_CTRL_START_EN (0x1)
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#define PHY_DLL_LOCK_DIFF 0x0
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#define DDR_CKE_CTRL_NORMAL 0x1
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#define PHY_EN_DYN_PWRDN (0x1 << 20)
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/* Micron MT47H128M16RT-25E */
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#define MT47H128M16RT25E_EMIF_READ_LATENCY 0x100005
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#define MT47H128M16RT25E_EMIF_TIM1 0x0666B3C9
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#define MT47H128M16RT25E_EMIF_TIM2 0x243631CA
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#define MT47H128M16RT25E_EMIF_TIM3 0x0000033F
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#define MT47H128M16RT25E_EMIF_SDCFG 0x41805332
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#define MT47H128M16RT25E_EMIF_SDREF 0x0000081a
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#define MT47H128M16RT25E_DLL_LOCK_DIFF 0x0
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#define MT47H128M16RT25E_RATIO 0x80
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#define MT47H128M16RT25E_INVERT_CLKOUT 0x00
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#define MT47H128M16RT25E_RD_DQS 0x12
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#define MT47H128M16RT25E_WR_DQS 0x00
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#define MT47H128M16RT25E_PHY_WRLVL 0x00
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#define MT47H128M16RT25E_PHY_GATELVL 0x00
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#define MT47H128M16RT25E_PHY_WR_DATA 0x40
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#define MT47H128M16RT25E_PHY_FIFO_WE 0x80
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#define MT47H128M16RT25E_PHY_RANK0_DELAY 0x1
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#define MT47H128M16RT25E_IOCTRL_VALUE 0x18B
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/* Micron MT41J128M16JT-125 */
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#define MT41J128MJT125_EMIF_READ_LATENCY 0x06
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#define MT41J128MJT125_EMIF_TIM1 0x0888A39B
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#define MT41J128MJT125_EMIF_TIM2 0x26337FDA
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#define MT41J128MJT125_EMIF_TIM3 0x501F830F
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#define MT41J128MJT125_EMIF_SDCFG 0x61C04AB2
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#define MT41J128MJT125_EMIF_SDREF 0x0000093B
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#define MT41J128MJT125_ZQ_CFG 0x50074BE4
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#define MT41J128MJT125_DLL_LOCK_DIFF 0x1
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#define MT41J128MJT125_RATIO 0x40
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#define MT41J128MJT125_INVERT_CLKOUT 0x1
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#define MT41J128MJT125_RD_DQS 0x3B
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#define MT41J128MJT125_WR_DQS 0x85
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#define MT41J128MJT125_PHY_WR_DATA 0xC1
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#define MT41J128MJT125_PHY_FIFO_WE 0x100
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#define MT41J128MJT125_IOCTRL_VALUE 0x18B
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/* Micron MT41J256M8HX-15E */
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#define MT41J256M8HX15E_EMIF_READ_LATENCY 0x06
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#define MT41J256M8HX15E_EMIF_TIM1 0x0888A39B
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#define MT41J256M8HX15E_EMIF_TIM2 0x26337FDA
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#define MT41J256M8HX15E_EMIF_TIM3 0x501F830F
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#define MT41J256M8HX15E_EMIF_SDCFG 0x61C04B32
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#define MT41J256M8HX15E_EMIF_SDREF 0x0000093B
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#define MT41J256M8HX15E_ZQ_CFG 0x50074BE4
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#define MT41J256M8HX15E_DLL_LOCK_DIFF 0x1
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#define MT41J256M8HX15E_RATIO 0x40
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#define MT41J256M8HX15E_INVERT_CLKOUT 0x1
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#define MT41J256M8HX15E_RD_DQS 0x3B
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#define MT41J256M8HX15E_WR_DQS 0x85
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#define MT41J256M8HX15E_PHY_WR_DATA 0xC1
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#define MT41J256M8HX15E_PHY_FIFO_WE 0x100
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#define MT41J256M8HX15E_IOCTRL_VALUE 0x18B
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/* Micron MT41K256M16HA-125E */
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#define MT41K256M16HA125E_EMIF_READ_LATENCY 0x100007
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#define MT41K256M16HA125E_EMIF_TIM1 0x0AAAD4DB
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#define MT41K256M16HA125E_EMIF_TIM2 0x266B7FDA
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#define MT41K256M16HA125E_EMIF_TIM3 0x501F867F
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#define MT41K256M16HA125E_EMIF_SDCFG 0x61C05332
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#define MT41K256M16HA125E_EMIF_SDREF 0xC30
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#define MT41K256M16HA125E_ZQ_CFG 0x50074BE4
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#define MT41K256M16HA125E_DLL_LOCK_DIFF 0x1
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#define MT41K256M16HA125E_RATIO 0x80
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#define MT41K256M16HA125E_INVERT_CLKOUT 0x0
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#define MT41K256M16HA125E_RD_DQS 0x38
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#define MT41K256M16HA125E_WR_DQS 0x44
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#define MT41K256M16HA125E_PHY_WR_DATA 0x7D
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#define MT41K256M16HA125E_PHY_FIFO_WE 0x94
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#define MT41K256M16HA125E_IOCTRL_VALUE 0x18B
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/* Micron MT41J512M8RH-125 on EVM v1.5 */
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#define MT41J512M8RH125_EMIF_READ_LATENCY 0x06
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#define MT41J512M8RH125_EMIF_TIM1 0x0888A39B
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#define MT41J512M8RH125_EMIF_TIM2 0x26517FDA
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#define MT41J512M8RH125_EMIF_TIM3 0x501F84EF
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#define MT41J512M8RH125_EMIF_SDCFG 0x61C04BB2
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#define MT41J512M8RH125_EMIF_SDREF 0x0000093B
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#define MT41J512M8RH125_ZQ_CFG 0x50074BE4
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#define MT41J512M8RH125_DLL_LOCK_DIFF 0x1
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#define MT41J512M8RH125_RATIO 0x80
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#define MT41J512M8RH125_INVERT_CLKOUT 0x0
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#define MT41J512M8RH125_RD_DQS 0x3B
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#define MT41J512M8RH125_WR_DQS 0x3C
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#define MT41J512M8RH125_PHY_FIFO_WE 0xA5
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#define MT41J512M8RH125_PHY_WR_DATA 0x74
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#define MT41J512M8RH125_IOCTRL_VALUE 0x18B
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/* Samsung K4B2G1646E-BIH9 */
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#define K4B2G1646EBIH9_EMIF_READ_LATENCY 0x06
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#define K4B2G1646EBIH9_EMIF_TIM1 0x0888A39B
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#define K4B2G1646EBIH9_EMIF_TIM2 0x2A04011A
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#define K4B2G1646EBIH9_EMIF_TIM3 0x501F820F
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#define K4B2G1646EBIH9_EMIF_SDCFG 0x61C24AB2
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#define K4B2G1646EBIH9_EMIF_SDREF 0x0000093B
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#define K4B2G1646EBIH9_ZQ_CFG 0x50074BE4
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#define K4B2G1646EBIH9_DLL_LOCK_DIFF 0x1
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#define K4B2G1646EBIH9_RATIO 0x40
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#define K4B2G1646EBIH9_INVERT_CLKOUT 0x1
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#define K4B2G1646EBIH9_RD_DQS 0x3B
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#define K4B2G1646EBIH9_WR_DQS 0x85
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#define K4B2G1646EBIH9_PHY_FIFO_WE 0x100
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#define K4B2G1646EBIH9_PHY_WR_DATA 0xC1
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#define K4B2G1646EBIH9_IOCTRL_VALUE 0x18B
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/**
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* Configure DMM
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*/
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void config_dmm(const struct dmm_lisa_map_regs *regs);
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/**
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* Configure SDRAM
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*/
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void config_sdram(const struct emif_regs *regs, int nr);
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/**
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* Set SDRAM timings
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*/
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void set_sdram_timings(const struct emif_regs *regs, int nr);
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/**
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* Configure DDR PHY
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*/
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void config_ddr_phy(const struct emif_regs *regs, int nr);
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void ddr_pll_config(unsigned int ddrpll_m);
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struct ddr_cmd_regs {
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unsigned int resv0[7];
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unsigned int cm0csratio; /* offset 0x01C */
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unsigned int resv1[2];
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unsigned int cm0dldiff; /* offset 0x028 */
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unsigned int cm0iclkout; /* offset 0x02C */
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unsigned int resv2[8];
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unsigned int cm1csratio; /* offset 0x050 */
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unsigned int resv3[2];
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unsigned int cm1dldiff; /* offset 0x05C */
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unsigned int cm1iclkout; /* offset 0x060 */
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unsigned int resv4[8];
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unsigned int cm2csratio; /* offset 0x084 */
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unsigned int resv5[2];
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unsigned int cm2dldiff; /* offset 0x090 */
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unsigned int cm2iclkout; /* offset 0x094 */
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unsigned int resv6[3];
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};
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struct ddr_data_regs {
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unsigned int dt0rdsratio0; /* offset 0x0C8 */
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unsigned int resv1[4];
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unsigned int dt0wdsratio0; /* offset 0x0DC */
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unsigned int resv2[4];
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unsigned int dt0wiratio0; /* offset 0x0F0 */
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unsigned int resv3;
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unsigned int dt0wimode0; /* offset 0x0F8 */
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unsigned int dt0giratio0; /* offset 0x0FC */
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unsigned int resv4;
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unsigned int dt0gimode0; /* offset 0x104 */
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unsigned int dt0fwsratio0; /* offset 0x108 */
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unsigned int resv5[4];
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unsigned int dt0dqoffset; /* offset 0x11C */
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unsigned int dt0wrsratio0; /* offset 0x120 */
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unsigned int resv6[4];
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unsigned int dt0rdelays0; /* offset 0x134 */
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unsigned int dt0dldiff0; /* offset 0x138 */
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unsigned int resv7[12];
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};
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/**
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* This structure represents the DDR registers on AM33XX devices.
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* We make use of DDR_PHY_BASE_ADDR2 to address the DATA1 registers that
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* correspond to DATA1 registers defined here.
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*/
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struct ddr_regs {
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unsigned int resv0[7];
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unsigned int cm0csratio; /* offset 0x01C */
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unsigned int resv1[2];
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unsigned int cm0dldiff; /* offset 0x028 */
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unsigned int cm0iclkout; /* offset 0x02C */
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unsigned int resv2[8];
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unsigned int cm1csratio; /* offset 0x050 */
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unsigned int resv3[2];
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unsigned int cm1dldiff; /* offset 0x05C */
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unsigned int cm1iclkout; /* offset 0x060 */
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unsigned int resv4[8];
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unsigned int cm2csratio; /* offset 0x084 */
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unsigned int resv5[2];
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unsigned int cm2dldiff; /* offset 0x090 */
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unsigned int cm2iclkout; /* offset 0x094 */
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unsigned int resv6[12];
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unsigned int dt0rdsratio0; /* offset 0x0C8 */
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unsigned int resv7[4];
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unsigned int dt0wdsratio0; /* offset 0x0DC */
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unsigned int resv8[4];
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unsigned int dt0wiratio0; /* offset 0x0F0 */
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unsigned int resv9;
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unsigned int dt0wimode0; /* offset 0x0F8 */
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unsigned int dt0giratio0; /* offset 0x0FC */
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unsigned int resv10;
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unsigned int dt0gimode0; /* offset 0x104 */
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unsigned int dt0fwsratio0; /* offset 0x108 */
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unsigned int resv11[4];
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unsigned int dt0dqoffset; /* offset 0x11C */
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unsigned int dt0wrsratio0; /* offset 0x120 */
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unsigned int resv12[4];
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unsigned int dt0rdelays0; /* offset 0x134 */
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unsigned int dt0dldiff0; /* offset 0x138 */
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};
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/**
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* Encapsulates DDR CMD control registers.
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*/
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struct cmd_control {
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unsigned long cmd0csratio;
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unsigned long cmd0csforce;
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unsigned long cmd0csdelay;
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unsigned long cmd0dldiff;
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unsigned long cmd0iclkout;
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unsigned long cmd1csratio;
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unsigned long cmd1csforce;
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unsigned long cmd1csdelay;
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unsigned long cmd1dldiff;
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unsigned long cmd1iclkout;
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unsigned long cmd2csratio;
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unsigned long cmd2csforce;
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unsigned long cmd2csdelay;
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unsigned long cmd2dldiff;
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unsigned long cmd2iclkout;
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};
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/**
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* Encapsulates DDR DATA registers.
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*/
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struct ddr_data {
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unsigned long datardsratio0;
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unsigned long datawdsratio0;
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unsigned long datawiratio0;
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unsigned long datagiratio0;
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unsigned long datafwsratio0;
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unsigned long datawrsratio0;
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unsigned long datauserank0delay;
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unsigned long datadldiff0;
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};
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/**
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* Configure DDR CMD control registers
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*/
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void config_cmd_ctrl(const struct cmd_control *cmd, int nr);
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/**
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* Configure DDR DATA registers
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*/
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void config_ddr_data(const struct ddr_data *data, int nr);
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/**
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* This structure represents the DDR io control on AM33XX devices.
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*/
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struct ddr_cmdtctrl {
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unsigned int cm0ioctl;
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unsigned int cm1ioctl;
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unsigned int cm2ioctl;
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unsigned int resv2[12];
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unsigned int dt0ioctl;
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unsigned int dt1ioctl;
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};
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/**
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* Configure DDR io control registers
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*/
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void config_io_ctrl(unsigned long val);
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struct ddr_ctrl {
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unsigned int ddrioctrl;
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unsigned int resv1[325];
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unsigned int ddrckectrl;
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};
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void config_ddr(unsigned int pll, unsigned int ioctrl,
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const struct ddr_data *data, const struct cmd_control *ctrl,
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const struct emif_regs *regs, int nr);
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#endif /* _DDR_DEFS_H */
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