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94bf34b172
The Denali NAND controller IP needs three clocks: - clk: controller core clock - clk_x: bus interface clock - ecc_clk: clock at which ECC circuitry is run Currently, only the first one (50MHz) is provided. The rest of the two clock ports must be connected to the 200MHz clock line. Add this. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
65 lines
2.7 KiB
C
65 lines
2.7 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2016-2017 Socionext Inc.
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* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
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*/
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#include "clk-uniphier.h"
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#define UNIPHIER_LD4_SYS_CLK_NAND(_id) \
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UNIPHIER_CLK_RATE(128, 50000000), \
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UNIPHIER_CLK_GATE((_id), 128, 0x2104, 2)
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#define UNIPHIER_LD11_SYS_CLK_NAND(_id) \
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UNIPHIER_CLK_RATE(128, 50000000), \
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UNIPHIER_CLK_GATE((_id), 128, 0x210c, 0)
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const struct uniphier_clk_data uniphier_pxs2_sys_clk_data[] = {
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#if defined(CONFIG_ARCH_UNIPHIER_LD4) || defined(CONFIG_ARCH_UNIPHIER_SLD8) ||\
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defined(CONFIG_ARCH_UNIPHIER_PRO4) || defined(CONFIG_ARCH_UNIPHIER_PRO5) ||\
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defined(CONFIG_ARCH_UNIPHIER_PXS2) || defined(CONFIG_ARCH_UNIPHIER_LD6B)
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UNIPHIER_LD4_SYS_CLK_NAND(2),
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UNIPHIER_CLK_RATE(3, 200000000),
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UNIPHIER_CLK_GATE_SIMPLE(6, 0x2104, 12), /* ether (Pro4, PXs2) */
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UNIPHIER_CLK_GATE_SIMPLE(7, 0x2104, 5), /* ether-gb (Pro4) */
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UNIPHIER_CLK_GATE_SIMPLE(8, 0x2104, 10), /* stdmac */
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UNIPHIER_CLK_GATE_SIMPLE(10, 0x2260, 0), /* ether-phy (Pro4) */
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UNIPHIER_CLK_GATE_SIMPLE(12, 0x2104, 6), /* gio (Pro4, Pro5) */
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UNIPHIER_CLK_GATE_SIMPLE(14, 0x2104, 16), /* usb30 (Pro4, Pro5, PXs2) */
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UNIPHIER_CLK_GATE_SIMPLE(15, 0x2104, 17), /* usb31 (Pro4, Pro5, PXs2) */
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UNIPHIER_CLK_GATE_SIMPLE(16, 0x2104, 19), /* usb30-phy (PXs2) */
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UNIPHIER_CLK_GATE_SIMPLE(20, 0x2104, 20), /* usb31-phy (PXs2) */
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{ /* sentinel */ }
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#endif
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};
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const struct uniphier_clk_data uniphier_ld20_sys_clk_data[] = {
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#if defined(CONFIG_ARCH_UNIPHIER_LD11) || defined(CONFIG_ARCH_UNIPHIER_LD20)
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UNIPHIER_LD11_SYS_CLK_NAND(2),
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UNIPHIER_CLK_RATE(3, 200000000),
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UNIPHIER_CLK_GATE_SIMPLE(6, 0x210c, 6), /* ether */
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UNIPHIER_CLK_GATE_SIMPLE(8, 0x210c, 8), /* stdmac */
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UNIPHIER_CLK_GATE_SIMPLE(14, 0x210c, 14), /* usb30 (LD20) */
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UNIPHIER_CLK_GATE_SIMPLE(16, 0x210c, 12), /* usb30-phy0 (LD20) */
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UNIPHIER_CLK_GATE_SIMPLE(17, 0x210c, 13), /* usb30-phy1 (LD20) */
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{ /* sentinel */ }
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#endif
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};
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const struct uniphier_clk_data uniphier_pxs3_sys_clk_data[] = {
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#if defined(CONFIG_ARCH_UNIPHIER_PXS3)
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UNIPHIER_LD11_SYS_CLK_NAND(2),
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UNIPHIER_CLK_RATE(3, 200000000),
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UNIPHIER_CLK_GATE_SIMPLE(6, 0x210c, 9), /* ether0 */
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UNIPHIER_CLK_GATE_SIMPLE(7, 0x210c, 10), /* ether1 */
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UNIPHIER_CLK_GATE_SIMPLE(12, 0x210c, 4), /* usb30 (gio0) */
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UNIPHIER_CLK_GATE_SIMPLE(13, 0x210c, 5), /* usb31-0 (gio1) */
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UNIPHIER_CLK_GATE_SIMPLE(14, 0x210c, 6), /* usb31-1 (gio1-1) */
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UNIPHIER_CLK_GATE_SIMPLE(16, 0x210c, 16), /* usb30-phy0 */
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UNIPHIER_CLK_GATE_SIMPLE(17, 0x210c, 18), /* usb30-phy1 */
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UNIPHIER_CLK_GATE_SIMPLE(18, 0x210c, 20), /* usb30-phy2 */
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UNIPHIER_CLK_GATE_SIMPLE(20, 0x210c, 17), /* usb31-phy0 */
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UNIPHIER_CLK_GATE_SIMPLE(21, 0x210c, 19), /* usb31-phy1 */
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{ /* sentinel */ }
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#endif
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};
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