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https://github.com/AsahiLinux/u-boot
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145 lines
5.1 KiB
C
145 lines
5.1 KiB
C
/*
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* DO NOT EDIT THIS FILE
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* This file is under version control at
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* svn://sources.blackfin.uclinux.org/toolchain/trunk/proc-defs/header-frags/
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* and can be replaced with that version at any time
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* DO NOT EDIT THIS FILE
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*
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* Copyright 2004-2011 Analog Devices Inc.
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* Licensed under the ADI BSD license.
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* https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd
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*/
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/* This file should be up to date with:
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* - Revision A, 02/18/2011; ADSP-BF504/BF504F/BF506F Blackfin Processor Anomaly List
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*/
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#if __SILICON_REVISION__ < 0
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# error will not work on BF506 silicon version
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#endif
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#ifndef _MACH_ANOMALY_H_
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#define _MACH_ANOMALY_H_
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/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
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#define ANOMALY_05000074 (1)
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/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
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#define ANOMALY_05000119 (1)
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/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
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#define ANOMALY_05000122 (1)
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/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
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#define ANOMALY_05000245 (1)
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/* Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock */
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#define ANOMALY_05000254 (1)
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/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
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#define ANOMALY_05000265 (1)
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/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
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#define ANOMALY_05000310 (1)
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/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
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#define ANOMALY_05000366 (1)
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/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
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#define ANOMALY_05000426 (1)
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/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
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#define ANOMALY_05000443 (1)
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/* UART IrDA Receiver Fails on Extended Bit Pulses */
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#define ANOMALY_05000447 (1)
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/* False Hardware Error when RETI Points to Invalid Memory */
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#define ANOMALY_05000461 (1)
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/* PLL Latches Incorrect Settings During Reset */
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#define ANOMALY_05000469 (1)
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/* Incorrect Default MSEL Value in PLL_CTL */
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#define ANOMALY_05000472 (1)
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/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */
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#define ANOMALY_05000473 (1)
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/* SPORT0 Data Transmit Error in Multi-Channel Mode with Internal Clock */
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#define ANOMALY_05000476 (1)
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/* TESTSET Instruction Cannot Be Interrupted */
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#define ANOMALY_05000477 (1)
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/* Disabling ACM During an Ongoing Transfer Can Lead to Undefined ACM Behavior */
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#define ANOMALY_05000478 (1)
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/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
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#define ANOMALY_05000481 (1)
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/* TWI Vbus Minimum Specification Can Be Violated under Certain Conditions */
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#define ANOMALY_05000486 (1)
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/* SPI Master Boot Can Fail Under Certain Conditions */
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#define ANOMALY_05000490 (1)
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/* Instruction Memory Stalls Can Cause IFLUSH to Fail */
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#define ANOMALY_05000491 (1)
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/* EXCPT Instruction May Be Lost If NMI Happens Simultaneously */
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#define ANOMALY_05000494 (1)
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/* Maximum Idd-deepsleep Specifications Can Be Exceeded under Certain Conditions */
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#define ANOMALY_05000495 (1)
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/* CNT_COMMAND Functionality Depends on CNT_IMASK Configuration */
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#define ANOMALY_05000498 (1)
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/* RXS Bit in SPI_STAT May Become Stuck In RX DMA Modes */
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#define ANOMALY_05000501 (1)
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/* Anomalies that don't exist on this proc */
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#define ANOMALY_05000099 (0)
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#define ANOMALY_05000120 (0)
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#define ANOMALY_05000125 (0)
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#define ANOMALY_05000149 (0)
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#define ANOMALY_05000158 (0)
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#define ANOMALY_05000171 (0)
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#define ANOMALY_05000179 (0)
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#define ANOMALY_05000182 (0)
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#define ANOMALY_05000183 (0)
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#define ANOMALY_05000189 (0)
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#define ANOMALY_05000198 (0)
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#define ANOMALY_05000202 (0)
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#define ANOMALY_05000215 (0)
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#define ANOMALY_05000219 (0)
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#define ANOMALY_05000220 (0)
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#define ANOMALY_05000227 (0)
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#define ANOMALY_05000230 (0)
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#define ANOMALY_05000231 (0)
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#define ANOMALY_05000233 (0)
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#define ANOMALY_05000234 (0)
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#define ANOMALY_05000242 (0)
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#define ANOMALY_05000244 (0)
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#define ANOMALY_05000248 (0)
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#define ANOMALY_05000250 (0)
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#define ANOMALY_05000257 (0)
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#define ANOMALY_05000261 (0)
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#define ANOMALY_05000263 (0)
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#define ANOMALY_05000266 (0)
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#define ANOMALY_05000273 (0)
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#define ANOMALY_05000274 (0)
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#define ANOMALY_05000278 (0)
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#define ANOMALY_05000281 (0)
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#define ANOMALY_05000283 (0)
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#define ANOMALY_05000285 (0)
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#define ANOMALY_05000287 (0)
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#define ANOMALY_05000301 (0)
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#define ANOMALY_05000305 (0)
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#define ANOMALY_05000307 (0)
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#define ANOMALY_05000311 (0)
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#define ANOMALY_05000312 (0)
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#define ANOMALY_05000315 (0)
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#define ANOMALY_05000323 (0)
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#define ANOMALY_05000353 (0)
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#define ANOMALY_05000357 (0)
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#define ANOMALY_05000362 (1)
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#define ANOMALY_05000363 (0)
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#define ANOMALY_05000364 (0)
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#define ANOMALY_05000371 (0)
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#define ANOMALY_05000380 (0)
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#define ANOMALY_05000383 (0)
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#define ANOMALY_05000386 (0)
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#define ANOMALY_05000389 (0)
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#define ANOMALY_05000400 (0)
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#define ANOMALY_05000402 (0)
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#define ANOMALY_05000412 (0)
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#define ANOMALY_05000432 (0)
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#define ANOMALY_05000440 (0)
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#define ANOMALY_05000448 (0)
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#define ANOMALY_05000456 (0)
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#define ANOMALY_05000450 (0)
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#define ANOMALY_05000465 (0)
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#define ANOMALY_05000467 (0)
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#define ANOMALY_05000474 (0)
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#define ANOMALY_05000475 (0)
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#define ANOMALY_05000480 (0)
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#define ANOMALY_05000485 (0)
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#endif
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