Sean Anderson 9472630337 riscv: Clear pending interrupts before enabling IPIs ... On some platforms (k210), the previous stage bootloader may have not cleared pending IPIs before transferring control to U-Boot. This can cause race conditions, as multiple harts all attempt to initialize the IPI controller at once. This patch clears IPIs before enabling them, ensuring that only one hart modifies shared memory at once. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>		2020-07-01 15:01:21 +08:00
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cpu	riscv: Clear pending interrupts before enabling IPIs	2020-07-01 15:01:21 +08:00
dts	riscv: sifive: fu540: add SPL configuration	2020-06-04 09:44:09 +08:00
include/asm	riscv: Add headers for asm/global_data.h	2020-07-01 15:01:21 +08:00
lib	riscv: sbi: Move sbi_probe_extension() out of CONFIG_SBI_V01	2020-06-04 09:44:21 +08:00
config.mk	kconfig / kbuild: Re-sync with Linux 4.19	2020-04-10 11:18:32 -04:00
Kconfig	riscv: cpu: fu540: Add support for cpu fu540	2020-06-04 09:44:09 +08:00
Makefile	riscv: add Kconfig entries for the code model	2018-12-18 09:56:26 +08:00