mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-17 02:08:38 +00:00
e53237aa53
Apple's M2 SoC very similar to the M1 and can use the same memory map. The keyboard/trackpad on the MacBook Pro (13-inch, M2, 2022) uses "dockchannel" as transport instead of SPI and needs a new driver. USB, NVMe, uart, framebuffer and watchdog are working with the existing drivers. Signed-off-by: Janne Grunau <j@jannau.net> Reviewed-by: Mark Kettenis <kettenis@openbsd.org>
504 lines
11 KiB
C
504 lines
11 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2021 Mark Kettenis <kettenis@openbsd.org>
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*/
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#include <common.h>
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#include <dm.h>
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#include <dm/uclass-internal.h>
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#include <efi_loader.h>
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#include <lmb.h>
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#include <asm/armv8/mmu.h>
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#include <asm/global_data.h>
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#include <asm/io.h>
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#include <asm/system.h>
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DECLARE_GLOBAL_DATA_PTR;
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/* Apple M1/M2 */
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static struct mm_region t8103_mem_map[] = {
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{
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/* I/O */
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.virt = 0x200000000,
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.phys = 0x200000000,
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.size = 2UL * SZ_1G,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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/* I/O */
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.virt = 0x380000000,
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.phys = 0x380000000,
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.size = SZ_1G,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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/* I/O */
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.virt = 0x500000000,
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.phys = 0x500000000,
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.size = SZ_1G,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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/* I/O */
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.virt = 0x680000000,
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.phys = 0x680000000,
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.size = SZ_512M,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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/* PCIE */
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.virt = 0x6a0000000,
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.phys = 0x6a0000000,
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.size = SZ_512M,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRE) |
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PTE_BLOCK_INNER_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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/* PCIE */
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.virt = 0x6c0000000,
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.phys = 0x6c0000000,
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.size = SZ_1G,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRE) |
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PTE_BLOCK_INNER_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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/* RAM */
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.virt = 0x800000000,
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.phys = 0x800000000,
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.size = 8UL * SZ_1G,
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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PTE_BLOCK_INNER_SHARE
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}, {
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/* Framebuffer */
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) |
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PTE_BLOCK_INNER_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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/* List terminator */
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0,
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}
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};
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/* Apple M1 Pro/Max */
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static struct mm_region t6000_mem_map[] = {
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{
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/* I/O */
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.virt = 0x280000000,
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.phys = 0x280000000,
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.size = SZ_1G,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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/* I/O */
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.virt = 0x380000000,
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.phys = 0x380000000,
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.size = SZ_1G,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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/* I/O */
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.virt = 0x580000000,
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.phys = 0x580000000,
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.size = SZ_512M,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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/* PCIE */
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.virt = 0x5a0000000,
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.phys = 0x5a0000000,
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.size = SZ_512M,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRE) |
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PTE_BLOCK_INNER_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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/* PCIE */
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.virt = 0x5c0000000,
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.phys = 0x5c0000000,
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.size = SZ_1G,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRE) |
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PTE_BLOCK_INNER_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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/* I/O */
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.virt = 0x700000000,
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.phys = 0x700000000,
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.size = SZ_1G,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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/* I/O */
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.virt = 0xb00000000,
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.phys = 0xb00000000,
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.size = SZ_1G,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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/* I/O */
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.virt = 0xf00000000,
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.phys = 0xf00000000,
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.size = SZ_1G,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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/* I/O */
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.virt = 0x1300000000,
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.phys = 0x1300000000,
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.size = SZ_1G,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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/* RAM */
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.virt = 0x10000000000,
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.phys = 0x10000000000,
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.size = 16UL * SZ_1G,
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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PTE_BLOCK_INNER_SHARE
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}, {
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/* Framebuffer */
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) |
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PTE_BLOCK_INNER_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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/* List terminator */
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0,
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}
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};
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/* Apple M1 Ultra */
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static struct mm_region t6002_mem_map[] = {
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{
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/* I/O */
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.virt = 0x280000000,
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.phys = 0x280000000,
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.size = SZ_1G,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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/* I/O */
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.virt = 0x380000000,
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.phys = 0x380000000,
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.size = SZ_1G,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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/* I/O */
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.virt = 0x580000000,
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.phys = 0x580000000,
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.size = SZ_512M,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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/* PCIE */
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.virt = 0x5a0000000,
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.phys = 0x5a0000000,
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.size = SZ_512M,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRE) |
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PTE_BLOCK_INNER_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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/* PCIE */
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.virt = 0x5c0000000,
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.phys = 0x5c0000000,
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.size = SZ_1G,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRE) |
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PTE_BLOCK_INNER_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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/* I/O */
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.virt = 0x700000000,
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.phys = 0x700000000,
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.size = SZ_1G,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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/* I/O */
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.virt = 0xb00000000,
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.phys = 0xb00000000,
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.size = SZ_1G,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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/* I/O */
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.virt = 0xf00000000,
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.phys = 0xf00000000,
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.size = SZ_1G,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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/* I/O */
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.virt = 0x1300000000,
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.phys = 0x1300000000,
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.size = SZ_1G,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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/* I/O */
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.virt = 0x2280000000,
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.phys = 0x2280000000,
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.size = SZ_1G,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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/* I/O */
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.virt = 0x2380000000,
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.phys = 0x2380000000,
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.size = SZ_1G,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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/* I/O */
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.virt = 0x2580000000,
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.phys = 0x2580000000,
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.size = SZ_512M,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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/* PCIE */
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.virt = 0x25a0000000,
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.phys = 0x25a0000000,
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.size = SZ_512M,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRE) |
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PTE_BLOCK_INNER_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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/* PCIE */
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.virt = 0x25c0000000,
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.phys = 0x25c0000000,
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.size = SZ_1G,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRE) |
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PTE_BLOCK_INNER_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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/* I/O */
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.virt = 0x2700000000,
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.phys = 0x2700000000,
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.size = SZ_1G,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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/* I/O */
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.virt = 0x2b00000000,
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.phys = 0x2b00000000,
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.size = SZ_1G,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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/* I/O */
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.virt = 0x2f00000000,
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.phys = 0x2f00000000,
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.size = SZ_1G,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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/* I/O */
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.virt = 0x3300000000,
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.phys = 0x3300000000,
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.size = SZ_1G,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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/* RAM */
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.virt = 0x10000000000,
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.phys = 0x10000000000,
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.size = 16UL * SZ_1G,
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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PTE_BLOCK_INNER_SHARE
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}, {
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/* Framebuffer */
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) |
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PTE_BLOCK_INNER_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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/* List terminator */
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0,
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}
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};
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struct mm_region *mem_map;
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int board_init(void)
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{
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return 0;
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}
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int dram_init(void)
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{
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return fdtdec_setup_mem_size_base();
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}
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int dram_init_banksize(void)
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{
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return fdtdec_setup_memory_banksize();
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}
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extern long fw_dtb_pointer;
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void *board_fdt_blob_setup(int *err)
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{
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/* Return DTB pointer passed by m1n1 */
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*err = 0;
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return (void *)fw_dtb_pointer;
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}
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void build_mem_map(void)
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{
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ofnode node;
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fdt_addr_t base;
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fdt_size_t size;
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int i;
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if (of_machine_is_compatible("apple,t8103") ||
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of_machine_is_compatible("apple,t8112"))
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mem_map = t8103_mem_map;
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else if (of_machine_is_compatible("apple,t6000"))
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mem_map = t6000_mem_map;
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else if (of_machine_is_compatible("apple,t6001"))
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mem_map = t6000_mem_map;
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else if (of_machine_is_compatible("apple,t6002"))
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mem_map = t6002_mem_map;
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else
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panic("Unsupported SoC\n");
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/* Find list terminator. */
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for (i = 0; mem_map[i].size || mem_map[i].attrs; i++)
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;
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/* Align RAM mapping to page boundaries */
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base = gd->bd->bi_dram[0].start;
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size = gd->bd->bi_dram[0].size;
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size += (base - ALIGN_DOWN(base, SZ_4K));
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base = ALIGN_DOWN(base, SZ_4K);
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size = ALIGN(size, SZ_4K);
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/* Update RAM mapping */
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mem_map[i - 2].virt = base;
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mem_map[i - 2].phys = base;
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mem_map[i - 2].size = size;
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node = ofnode_path("/chosen/framebuffer");
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if (!ofnode_valid(node))
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return;
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base = ofnode_get_addr_size(node, "reg", &size);
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if (base == FDT_ADDR_T_NONE)
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return;
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/* Align framebuffer mapping to page boundaries */
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size += (base - ALIGN_DOWN(base, SZ_4K));
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base = ALIGN_DOWN(base, SZ_4K);
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size = ALIGN(size, SZ_4K);
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/* Add framebuffer mapping */
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mem_map[i - 1].virt = base;
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mem_map[i - 1].phys = base;
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mem_map[i - 1].size = size;
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}
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void enable_caches(void)
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{
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build_mem_map();
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icache_enable();
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dcache_enable();
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}
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u64 get_page_table_size(void)
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{
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return SZ_256K;
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}
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#define KERNEL_COMP_SIZE SZ_128M
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int board_late_init(void)
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{
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struct lmb lmb;
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u32 status = 0;
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lmb_init_and_reserve(&lmb, gd->bd, (void *)gd->fdt_blob);
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/* somewhat based on the Linux Kernel boot requirements:
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* align by 2M and maximal FDT size 2M
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*/
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status |= env_set_hex("loadaddr", lmb_alloc(&lmb, SZ_1G, SZ_2M));
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status |= env_set_hex("fdt_addr_r", lmb_alloc(&lmb, SZ_2M, SZ_2M));
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status |= env_set_hex("kernel_addr_r", lmb_alloc(&lmb, SZ_128M, SZ_2M));
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status |= env_set_hex("ramdisk_addr_r", lmb_alloc(&lmb, SZ_1G, SZ_2M));
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status |= env_set_hex("kernel_comp_addr_r",
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lmb_alloc(&lmb, KERNEL_COMP_SIZE, SZ_2M));
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status |= env_set_hex("kernel_comp_size", KERNEL_COMP_SIZE);
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status |= env_set_hex("scriptaddr", lmb_alloc(&lmb, SZ_4M, SZ_2M));
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status |= env_set_hex("pxefile_addr_r", lmb_alloc(&lmb, SZ_4M, SZ_2M));
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if (status)
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log_warning("late_init: Failed to set run time variables\n");
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return 0;
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}
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int ft_board_setup(void *blob, struct bd_info *bd)
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{
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struct udevice *dev;
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const char *stdoutname;
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int node, ret;
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/*
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* Modify the "stdout-path" property under "/chosen" to point
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* at "/chosen/framebuffer if a keyboard is available and
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* we're not running under the m1n1 hypervisor.
|
|
* Developers can override this behaviour by dropping
|
|
* "vidconsole" from the "stdout" environment variable.
|
|
*/
|
|
|
|
/* EL1 means we're running under the m1n1 hypervisor. */
|
|
if (current_el() == 1)
|
|
return 0;
|
|
|
|
ret = uclass_find_device(UCLASS_KEYBOARD, 0, &dev);
|
|
if (ret < 0)
|
|
return 0;
|
|
|
|
stdoutname = env_get("stdout");
|
|
if (!stdoutname || !strstr(stdoutname, "vidconsole"))
|
|
return 0;
|
|
|
|
/* Make sure we actually have a framebuffer. */
|
|
node = fdt_path_offset(blob, "/chosen/framebuffer");
|
|
if (node < 0 || !fdtdec_get_is_enabled(blob, node))
|
|
return 0;
|
|
|
|
node = fdt_path_offset(blob, "/chosen");
|
|
if (node < 0)
|
|
return 0;
|
|
fdt_setprop_string(blob, node, "stdout-path", "/chosen/framebuffer");
|
|
|
|
return 0;
|
|
}
|