mirror of
https://github.com/AsahiLinux/u-boot
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55d1537c5b
The Bosch ACC (Air Center Control) Board is based on the i.MX6D.
The device tree is copied from Linux, see [1]. The only difference
compared to the Linux DT is the removal of usbphynop properties. They are
defined in the Linux version of imx6qdl.dtsi, but not in the u-boot
version.
[1] Commit 6192cf8ac082 from
git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux.git
Signed-off-by: Philip Oberfichtner <pro@denx.de>
755 lines
19 KiB
C
755 lines
19 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (c) 2017 DENX Software Engineering GmbH, Heiko Schocher <hs@denx.de>
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* Copyright (c) 2019 Bosch Thermotechnik GmbH
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* Copyright (c) 2022 DENX Software Engineering GmbH, Philip Oberfichtner <pro@denx.de>
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*/
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#include <common.h>
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#include <bootstage.h>
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#include <dm.h>
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#include <dm/platform_data/serial_mxc.h>
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#include <dm/device-internal.h>
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#include <env.h>
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#include <env_internal.h>
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#include <hang.h>
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#include <init.h>
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#include <linux/delay.h>
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#include <mmc.h>
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#include <asm/io.h>
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#include <asm/gpio.h>
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#include <linux/sizes.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/crm_regs.h>
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#include <asm/arch/iomux.h>
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#include <asm/arch/mx6-pins.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/mach-imx/iomux-v3.h>
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#include <usb.h>
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#include <usb/ehci-ci.h>
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#include <fuse.h>
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#include <watchdog.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define GPIO_ACC_PLAT_DETECT IMX_GPIO_NR(5, 9)
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#define GPIO_ACC_RAM_VOLT_DETECT IMX_GPIO_NR(5, 0)
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#define GPIO_BUZZER IMX_GPIO_NR(1, 18)
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#define GPIO_LAN1_RESET IMX_GPIO_NR(4, 27)
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#define GPIO_LAN2_RESET IMX_GPIO_NR(4, 19)
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#define GPIO_LAN3_RESET IMX_GPIO_NR(4, 18)
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#define GPIO_USB_HUB_RESET IMX_GPIO_NR(5, 5)
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#define GPIO_EXP_RS485_RESET IMX_GPIO_NR(4, 16)
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#define GPIO_TOUCH_RESET IMX_GPIO_NR(1, 20)
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#define BOARD_INFO_MAGIC 0x19730517
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struct board_info {
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int magic;
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int board;
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int rev;
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};
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static struct board_info *detect_board(void);
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#define PFID_BOARD_ACC 0xe
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static const char * const name_board[] = {
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[PFID_BOARD_ACC] = "ACC",
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};
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#define PFID_REV_22 0x8
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#define PFID_REV_21 0x9
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#define PFID_REV_20 0xa
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#define PFID_REV_14 0xb
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#define PFID_REV_13 0xc
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#define PFID_REV_12 0xd
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#define PFID_REV_11 0xe
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#define PFID_REV_10 0xf
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static const char * const name_revision[] = {
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[0 ... PFID_REV_10] = "Unknown",
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[PFID_REV_10] = "1.0",
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[PFID_REV_11] = "1.1",
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[PFID_REV_12] = "1.2",
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[PFID_REV_13] = "1.3",
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[PFID_REV_14] = "1.4",
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[PFID_REV_20] = "2.0",
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[PFID_REV_21] = "2.1",
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[PFID_REV_22] = "2.2",
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};
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/*
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* NXP Reset Default: 0x0001B0B0
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* - Schmitt trigger input (PAD_CTL_HYS)
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* - 100K Ohm Pull Up (PAD_CTL_PUS_100K_UP)
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* - Pull Enabled (PAD_CTL_PUE)
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* - Pull/Keeper Enabled (PAD_CTL_PKE)
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* - CMOS output (No PAD_CTL_ODE)
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* - Medium Speed (PAD_CTL_SPEED_MED)
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* - 40 Ohm drive strength (PAD_CTL_DSE_40ohm)
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* - Slow (PAD_CTL_SRE_SLOW)
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*/
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/* Input, no pull up/down: 0x0x000100B0 */
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#define GPIN_PAD_CTRL (PAD_CTL_HYS \
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| PAD_CTL_SPEED_MED \
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| PAD_CTL_DSE_40ohm \
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| PAD_CTL_SRE_SLOW)
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/* Input, pull up: 0x0x0001B0B0 */
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#define GPIN_PU_PAD_CTRL (PAD_CTL_HYS \
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| PAD_CTL_PUS_100K_UP \
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| PAD_CTL_PUE \
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| PAD_CTL_PKE \
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| PAD_CTL_SPEED_MED \
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| PAD_CTL_DSE_40ohm \
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| PAD_CTL_SRE_SLOW)
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/* Input, pull down: 0x0x000130B0 */
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#define GPIN_PD_PAD_CTRL (PAD_CTL_HYS \
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| PAD_CTL_PUS_100K_DOWN \
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| PAD_CTL_PUE \
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| PAD_CTL_PKE \
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| PAD_CTL_SPEED_MED \
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| PAD_CTL_DSE_40ohm \
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| PAD_CTL_SRE_SLOW)
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static const iomux_v3_cfg_t board_detect_pads[] = {
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/* Platform detect */
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IOMUX_PADS(PAD_DISP0_DAT15__GPIO5_IO09 | MUX_PAD_CTRL(GPIN_PAD_CTRL)),
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/* RAM Volt detect */
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IOMUX_PADS(PAD_EIM_WAIT__GPIO5_IO00 | MUX_PAD_CTRL(GPIN_PAD_CTRL)),
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/* PFID 0..9 */
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IOMUX_PADS(PAD_NANDF_D0__GPIO2_IO00 | MUX_PAD_CTRL(GPIN_PAD_CTRL)),
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IOMUX_PADS(PAD_NANDF_D1__GPIO2_IO01 | MUX_PAD_CTRL(GPIN_PAD_CTRL)),
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IOMUX_PADS(PAD_NANDF_D2__GPIO2_IO02 | MUX_PAD_CTRL(GPIN_PAD_CTRL)),
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IOMUX_PADS(PAD_NANDF_D3__GPIO2_IO03 | MUX_PAD_CTRL(GPIN_PAD_CTRL)),
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IOMUX_PADS(PAD_NANDF_D4__GPIO2_IO04 | MUX_PAD_CTRL(GPIN_PAD_CTRL)),
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IOMUX_PADS(PAD_NANDF_D5__GPIO2_IO05 | MUX_PAD_CTRL(GPIN_PAD_CTRL)),
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IOMUX_PADS(PAD_NANDF_D6__GPIO2_IO06 | MUX_PAD_CTRL(GPIN_PAD_CTRL)),
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IOMUX_PADS(PAD_NANDF_D7__GPIO2_IO07 | MUX_PAD_CTRL(GPIN_PAD_CTRL)),
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IOMUX_PADS(PAD_NANDF_CS3__GPIO6_IO16 | MUX_PAD_CTRL(GPIN_PAD_CTRL)),
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IOMUX_PADS(PAD_NANDF_CS1__GPIO6_IO14 | MUX_PAD_CTRL(GPIN_PAD_CTRL)),
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/* Manufacturer */
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IOMUX_PADS(PAD_EIM_A24__GPIO5_IO04 | MUX_PAD_CTRL(GPIN_PAD_CTRL)),
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/* Redundant */
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IOMUX_PADS(PAD_NANDF_CS2__GPIO6_IO15 | MUX_PAD_CTRL(GPIN_PU_PAD_CTRL))
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};
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static int gpio_acc_pfid[] = {
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IMX_GPIO_NR(2, 0),
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IMX_GPIO_NR(2, 1),
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IMX_GPIO_NR(2, 2),
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IMX_GPIO_NR(2, 3),
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IMX_GPIO_NR(2, 4),
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IMX_GPIO_NR(6, 14),
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IMX_GPIO_NR(6, 15),
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IMX_GPIO_NR(2, 5),
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IMX_GPIO_NR(2, 6),
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IMX_GPIO_NR(2, 7),
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IMX_GPIO_NR(6, 16),
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IMX_GPIO_NR(5, 4),
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};
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static int init_gpio(int nr)
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{
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int ret;
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ret = gpio_request(nr, "");
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if (ret != 0) {
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printf("Could not request gpio nr: %d\n", nr);
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hang();
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}
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ret = gpio_direction_input(nr);
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if (ret != 0) {
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printf("Could not set gpio nr: %d to input\n", nr);
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hang();
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}
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return 0;
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}
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/*
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* We want to detect the board type only once in SPL,
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* so we store the board_info struct at beginning in IRAM.
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*
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* U-Boot itself can read it also, and do not need again
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* to detect board type.
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*
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*/
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static struct board_info *detect_board(void)
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{
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struct board_info *binfo = (struct board_info *)IRAM_BASE_ADDR;
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int i;
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if (binfo->magic == BOARD_INFO_MAGIC)
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return binfo;
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puts("Board: ");
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SETUP_IOMUX_PADS(board_detect_pads);
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init_gpio(GPIO_ACC_PLAT_DETECT);
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if (gpio_get_value(GPIO_ACC_PLAT_DETECT)) {
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puts("not supported");
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hang();
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} else {
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puts("Bosch ");
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}
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for (i = 0; i < sizeof(gpio_acc_pfid) / sizeof(int); i++)
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init_gpio(gpio_acc_pfid[i]);
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binfo->board = gpio_get_value(gpio_acc_pfid[0]) << 0 |
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gpio_get_value(gpio_acc_pfid[1]) << 1 |
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gpio_get_value(gpio_acc_pfid[2]) << 2 |
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gpio_get_value(gpio_acc_pfid[11]) << 3;
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printf("%s ", name_board[binfo->board]);
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binfo->rev = gpio_get_value(gpio_acc_pfid[7]) << 0 |
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gpio_get_value(gpio_acc_pfid[8]) << 1 |
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gpio_get_value(gpio_acc_pfid[9]) << 2 |
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gpio_get_value(gpio_acc_pfid[10]) << 3;
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printf("rev: %s\n", name_revision[binfo->rev]);
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binfo->magic = BOARD_INFO_MAGIC;
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return binfo;
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}
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static void unset_early_gpio(void)
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{
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init_gpio(GPIO_LAN1_RESET);
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init_gpio(GPIO_LAN2_RESET);
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init_gpio(GPIO_LAN3_RESET);
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init_gpio(GPIO_USB_HUB_RESET);
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init_gpio(GPIO_EXP_RS485_RESET);
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init_gpio(GPIO_TOUCH_RESET);
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gpio_set_value(GPIO_LAN1_RESET, 1);
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gpio_set_value(GPIO_LAN2_RESET, 1);
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gpio_set_value(GPIO_LAN3_RESET, 1);
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gpio_set_value(GPIO_USB_HUB_RESET, 1);
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gpio_set_value(GPIO_EXP_RS485_RESET, 1);
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gpio_set_value(GPIO_TOUCH_RESET, 1);
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}
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enum env_location env_get_location(enum env_operation op, int prio)
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{
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if (op == ENVOP_SAVE || op == ENVOP_ERASE)
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return ENVL_MMC;
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switch (prio) {
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case 0:
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return ENVL_NOWHERE;
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case 1:
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return ENVL_MMC;
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}
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return ENVL_UNKNOWN;
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}
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int board_late_init(void)
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{
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struct board_info *binfo = detect_board();
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switch (binfo->board) {
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case PFID_BOARD_ACC:
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env_set("bootconf", "conf-imx6q-bosch-acc.dtb");
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break;
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default:
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printf("Unknown board %d\n", binfo->board);
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break;
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}
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unset_early_gpio();
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return 0;
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}
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int board_init(void)
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{
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/* Address of boot parameters */
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gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
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return 0;
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}
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int dram_init(void)
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{
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gd->ram_size = imx_ddr_size();
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return 0;
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}
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#if IS_ENABLED(CONFIG_SPL_BUILD)
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#include <asm/arch/crm_regs.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/iomux.h>
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#include <asm/arch/mx6-ddr.h>
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#include <asm/arch/mx6-pins.h>
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#include <asm/arch/sys_proto.h>
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#include <spl.h>
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/* Early
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* - Buzzer -> GPIO IN, Pull-Down (PWM enabled by Kernel later-on, lacks of an
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* external pull-down resistor)
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* - Touch clean reset on every boot
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* - Ethernet(s), USB Hub, Expansion RS485 -> Clean reset on each u-boot init
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*/
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static const iomux_v3_cfg_t early_pads[] = {
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IOMUX_PADS(PAD_SD1_CMD__GPIO1_IO18 | MUX_PAD_CTRL(GPIN_PD_PAD_CTRL)), /* Buzzer PWM */
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IOMUX_PADS(PAD_DISP0_DAT6__GPIO4_IO27 | MUX_PAD_CTRL(GPIN_PD_PAD_CTRL)), /* #FEC_RESET_B */
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IOMUX_PADS(PAD_DI0_PIN2__GPIO4_IO18 | MUX_PAD_CTRL(GPIN_PD_PAD_CTRL)), /* #ETH1_RESET */
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IOMUX_PADS(PAD_DI0_PIN3__GPIO4_IO19 | MUX_PAD_CTRL(GPIN_PD_PAD_CTRL)), /* #ETH2_RESET */
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IOMUX_PADS(PAD_DISP0_DAT11__GPIO5_IO05 | MUX_PAD_CTRL(GPIN_PD_PAD_CTRL)), /* #USB Reset */
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IOMUX_PADS(PAD_DI0_DISP_CLK__GPIO4_IO16 | MUX_PAD_CTRL(GPIN_PD_PAD_CTRL)), /* #UART_RESET */
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IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20 | MUX_PAD_CTRL(GPIN_PD_PAD_CTRL)), /* #CTOUCH_RESET */
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};
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static void setup_iomux_early(void)
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{
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SETUP_IOMUX_PADS(early_pads);
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}
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static void set_early_gpio(void)
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{
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init_gpio(GPIO_BUZZER);
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init_gpio(GPIO_LAN1_RESET);
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init_gpio(GPIO_LAN2_RESET);
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init_gpio(GPIO_LAN3_RESET);
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init_gpio(GPIO_USB_HUB_RESET);
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init_gpio(GPIO_EXP_RS485_RESET);
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init_gpio(GPIO_TOUCH_RESET);
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/* Reset signals are active low */
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gpio_set_value(GPIO_BUZZER, 0);
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gpio_set_value(GPIO_LAN1_RESET, 0);
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gpio_set_value(GPIO_LAN2_RESET, 0);
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gpio_set_value(GPIO_LAN3_RESET, 0);
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gpio_set_value(GPIO_USB_HUB_RESET, 0);
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gpio_set_value(GPIO_EXP_RS485_RESET, 0);
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gpio_set_value(GPIO_TOUCH_RESET, 0);
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}
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/* UART */
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#define UART_PAD_CTRL \
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(PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
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PAD_CTL_SRE_FAST | PAD_CTL_HYS)
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#undef UART_PAD_CTRL
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#define UART_PAD_CTRL 0x1b0b1
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static const iomux_v3_cfg_t uart2_pads[] = {
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IOMUX_PADS(PAD_SD3_DAT4__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
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IOMUX_PADS(PAD_SD3_DAT5__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
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IOMUX_PADS(PAD_SD3_CMD__UART2_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL)),
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IOMUX_PADS(PAD_SD3_CLK__UART2_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL)),
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};
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static void setup_iomux_uart(void)
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{
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SETUP_IOMUX_PADS(uart2_pads);
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}
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void spl_board_init(void)
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{
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}
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static const struct mx6dq_iomux_ddr_regs acc_mx6d_ddr_ioregs = {
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.dram_sdclk_0 = 0x00008038,
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.dram_sdclk_1 = 0x00008038,
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.dram_cas = 0x00008028,
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.dram_ras = 0x00008028,
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.dram_reset = 0x00000028,
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.dram_sdcke0 = 0x00003000,
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.dram_sdcke1 = 0x00003000,
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.dram_sdba2 = 0x00008000,
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.dram_sdodt0 = 0x00000028,
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.dram_sdodt1 = 0x00000028,
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.dram_sdqs0 = 0x00008038,
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.dram_sdqs1 = 0x00008038,
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.dram_sdqs2 = 0x00008038,
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.dram_sdqs3 = 0x00008038,
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.dram_sdqs4 = 0x00008038,
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.dram_sdqs5 = 0x00008038,
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.dram_sdqs6 = 0x00008038,
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.dram_sdqs7 = 0x00008038,
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.dram_dqm0 = 0x00008038,
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.dram_dqm1 = 0x00008038,
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.dram_dqm2 = 0x00008038,
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.dram_dqm3 = 0x00008038,
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.dram_dqm4 = 0x00008038,
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.dram_dqm5 = 0x00008038,
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.dram_dqm6 = 0x00008038,
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.dram_dqm7 = 0x00008038,
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};
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static const struct mx6dq_iomux_grp_regs acc_mx6d_grp_ioregs = {
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.grp_ddr_type = 0x000C0000,
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.grp_ddrmode_ctl = 0x00020000,
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.grp_ddrpke = 0x00000000,
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.grp_addds = 0x00000030,
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.grp_ctlds = 0x00000028,
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.grp_ddrmode = 0x00020000,
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.grp_b0ds = 0x00000038,
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.grp_b1ds = 0x00000038,
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.grp_b2ds = 0x00000038,
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.grp_b3ds = 0x00000038,
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.grp_b4ds = 0x00000038,
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.grp_b5ds = 0x00000038,
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.grp_b6ds = 0x00000038,
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.grp_b7ds = 0x00000038,
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};
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static const struct mx6_mmdc_calibration acc_mx6d_mmdc_calib = {
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.p0_mpwldectrl0 = 0x0020001F,
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.p0_mpwldectrl1 = 0x00280021,
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.p1_mpwldectrl0 = 0x00120028,
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.p1_mpwldectrl1 = 0x000D001F,
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.p0_mpdgctrl0 = 0x43340342,
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.p0_mpdgctrl1 = 0x03300325,
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.p1_mpdgctrl0 = 0x4334033E,
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.p1_mpdgctrl1 = 0x03280270,
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.p0_mprddlctl = 0x46373B3E,
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.p1_mprddlctl = 0x3B383544,
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.p0_mpwrdlctl = 0x36383E40,
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.p1_mpwrdlctl = 0x4030433A,
|
|
};
|
|
|
|
/* Micron MT41K128M16JT-125 (standard - 1600,CL=11)
|
|
* !!! i.MX6 does NOT support data rates higher than DDR3-1066 !!!
|
|
* So this setting is actually invalid!
|
|
*
|
|
static const struct mx6_ddr3_cfg acc_mx6d_mem_ddr3_1600 = {
|
|
.mem_speed = 1600,
|
|
.density = 2,
|
|
.width = 16,
|
|
.banks = 8,
|
|
.rowaddr = 14,
|
|
.coladdr = 10,
|
|
.pagesz = 2,
|
|
.trcd = 1375,
|
|
.trcmin = 4875,
|
|
.trasmin = 3500,
|
|
.SRT = 0,
|
|
};
|
|
*/
|
|
|
|
/* Micron MT41K128M16JT-125 is backward-compatible with 1333,CL=9 (-15E) and 1066,CL=7 (-187E)
|
|
* Lowering to 1066 saves on ACC ~0.25 Watt at DC In with negligible performance loss
|
|
* width set to 64, as four chips are used on acc (4 * 16 = 64)
|
|
*/
|
|
static const struct mx6_ddr3_cfg acc_mx6d_mem_ddr3_1066 = {
|
|
.mem_speed = 1066,
|
|
.density = 2,
|
|
.width = 64,
|
|
.banks = 8,
|
|
.rowaddr = 14,
|
|
.coladdr = 10,
|
|
.pagesz = 2,
|
|
.trcd = 1313, // 13.125ns
|
|
.trcmin = 5063, // 50.625ns
|
|
.trasmin = 3750, // 37.5ns
|
|
.SRT = 0, // Set to 1 for temperatures above 85°C
|
|
};
|
|
|
|
static const struct mx6_ddr_sysinfo acc_mx6d_ddr_info = {
|
|
.ddr_type = DDR_TYPE_DDR3,
|
|
/* width of data bus:0=16,1=32,2=64 */
|
|
.dsize = 2,
|
|
.cs_density = 32, /* 32Gb per CS */
|
|
.ncs = 1, /* single chip select */
|
|
.cs1_mirror = 0,
|
|
.rtt_wr = 1, /* DDR3_RTT_60_OHM, RTT_Wr = RZQ/4 */
|
|
.rtt_nom = 1, /* DDR3_RTT_60_OHM, RTT_Nom = RZQ/4 */
|
|
.walat = 0, /* Write additional latency */
|
|
.ralat = 5, /* Read additional latency */
|
|
.mif3_mode = 3, /* Command prediction working mode */
|
|
.bi_on = 1, /* Bank interleaving enabled */
|
|
.sde_to_rst = 0x33, /* 14 cycles, 200us (JEDEC default) */
|
|
.rst_to_cke = 0x33, /* 33 cycles, 500us (JEDEC default) */
|
|
};
|
|
|
|
#define ACC_SPREAD_SPECTRUM_STOP 0x0fa
|
|
#define ACC_SPREAD_SPECTRUM_STEP 0x001
|
|
#define ACC_SPREAD_SPECTRUM_DENOM 0x190
|
|
|
|
static void ccgr_init(void)
|
|
{
|
|
struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
|
|
|
|
/* Turn clocks on/off */
|
|
writel(0x00C0000F, &ccm->CCGR0);
|
|
writel(0x0030FC00, &ccm->CCGR1);
|
|
writel(0x03FF0033, &ccm->CCGR2);
|
|
writel(0x3FF3300F, &ccm->CCGR3);
|
|
writel(0x0003C300, &ccm->CCGR4);
|
|
writel(0x0F3000C3, &ccm->CCGR5);
|
|
writel(0x00000FFF, &ccm->CCGR6);
|
|
|
|
/* Enable spread spectrum */
|
|
writel(BM_ANADIG_PLL_528_SS_ENABLE |
|
|
BF_ANADIG_PLL_528_SS_STOP(ACC_SPREAD_SPECTRUM_STOP) |
|
|
BF_ANADIG_PLL_528_SS_STEP(ACC_SPREAD_SPECTRUM_STEP),
|
|
&ccm->analog_pll_528_ss);
|
|
|
|
writel(BF_ANADIG_PLL_528_DENOM_B(ACC_SPREAD_SPECTRUM_DENOM),
|
|
&ccm->analog_pll_528_denom);
|
|
}
|
|
|
|
/* MMC board initialization is needed till adding DM support in SPL */
|
|
#if IS_ENABLED(CONFIG_FSL_ESDHC_IMX) && !IS_ENABLED(CONFIG_DM_MMC)
|
|
#include <mmc.h>
|
|
#include <fsl_esdhc_imx.h>
|
|
|
|
static const iomux_v3_cfg_t usdhc2_pads[] = {
|
|
IOMUX_PADS(PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(0x00017069)),
|
|
IOMUX_PADS(PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(0x00010038)),
|
|
IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(0x00017069)),
|
|
IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(0x00017069)),
|
|
IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(0x00017069)),
|
|
IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(0x00017069)),
|
|
IOMUX_PADS(PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(0x0001B0B0)), /* CD */
|
|
};
|
|
|
|
static const iomux_v3_cfg_t usdhc4_pads[] = {
|
|
IOMUX_PADS(PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(0x00017059)),
|
|
IOMUX_PADS(PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(0x00010059)),
|
|
IOMUX_PADS(PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(0x00017059)),
|
|
IOMUX_PADS(PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(0x00017059)),
|
|
IOMUX_PADS(PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(0x00017059)),
|
|
IOMUX_PADS(PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(0x00017059)),
|
|
IOMUX_PADS(PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(0x00017059)),
|
|
IOMUX_PADS(PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(0x00017059)),
|
|
IOMUX_PADS(PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(0x00017059)),
|
|
IOMUX_PADS(PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(0x00017059)),
|
|
};
|
|
|
|
struct fsl_esdhc_cfg usdhc_cfg[2] = {
|
|
{USDHC2_BASE_ADDR, 1, 4},
|
|
{USDHC4_BASE_ADDR, 1, 8},
|
|
};
|
|
|
|
#define USDHC2_CD_GPIO IMX_GPIO_NR(1, 4)
|
|
|
|
int board_mmc_getcd(struct mmc *mmc)
|
|
{
|
|
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
|
|
int ret = 0;
|
|
|
|
detect_board();
|
|
|
|
switch (cfg->esdhc_base) {
|
|
case USDHC2_BASE_ADDR:
|
|
return !gpio_get_value(USDHC2_CD_GPIO);
|
|
case USDHC4_BASE_ADDR:
|
|
return 1; /* eMMC always present */
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
int board_mmc_init(struct bd_info *bis)
|
|
{
|
|
int i, ret;
|
|
|
|
gpio_direction_input(USDHC2_CD_GPIO);
|
|
/*
|
|
* According to the board_mmc_init() the following map is done:
|
|
* (U-boot device node) (Physical Port)
|
|
* mmc0 USDHC2
|
|
* mmc1 USDHC4
|
|
*/
|
|
for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
|
|
switch (i) {
|
|
case 0:
|
|
SETUP_IOMUX_PADS(usdhc2_pads);
|
|
usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
|
|
break;
|
|
case 1:
|
|
SETUP_IOMUX_PADS(usdhc4_pads);
|
|
usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
|
|
break;
|
|
default:
|
|
printf("Warning - USDHC%d controller not supporting\n",
|
|
i + 1);
|
|
return 0;
|
|
}
|
|
|
|
ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
|
|
if (ret) {
|
|
printf("Warning: failed to initialize mmc dev %d\n", i);
|
|
return ret;
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
#endif
|
|
|
|
void board_boot_order(u32 *spl_boot_list)
|
|
{
|
|
u32 bmode = imx6_src_get_boot_mode();
|
|
u8 boot_dev = BOOT_DEVICE_MMC1;
|
|
|
|
detect_board();
|
|
|
|
switch ((bmode & IMX6_BMODE_MASK) >> IMX6_BMODE_SHIFT) {
|
|
case IMX6_BMODE_SD:
|
|
case IMX6_BMODE_ESD:
|
|
/* SD/eSD - BOOT_DEVICE_MMC1 */
|
|
if (IS_ENABLED(CONFIG_SYS_BOOT_EMMC)) {
|
|
/*
|
|
* boot from SD is not allowed, if boot from eMMC is
|
|
* configured.
|
|
*/
|
|
puts("SD boot not allowed\n");
|
|
spl_boot_list[0] = BOOT_DEVICE_NONE;
|
|
return;
|
|
}
|
|
|
|
boot_dev = BOOT_DEVICE_MMC1;
|
|
break;
|
|
|
|
case IMX6_BMODE_MMC:
|
|
case IMX6_BMODE_EMMC:
|
|
/* MMC/eMMC */
|
|
boot_dev = BOOT_DEVICE_MMC2;
|
|
break;
|
|
default:
|
|
/* Default - BOOT_DEVICE_MMC1 */
|
|
printf("Wrong board boot order\n");
|
|
break;
|
|
}
|
|
|
|
spl_boot_list[0] = boot_dev;
|
|
}
|
|
|
|
static void setup_ddr(void)
|
|
{
|
|
struct board_info *binfo = detect_board();
|
|
|
|
switch (binfo->rev) {
|
|
case PFID_REV_20:
|
|
case PFID_REV_21:
|
|
case PFID_REV_22:
|
|
default:
|
|
/* Rev 2 board has i.MX6 Dual with 64-bit RAM */
|
|
mx6dq_dram_iocfg(acc_mx6d_mem_ddr3_1066.width,
|
|
&acc_mx6d_ddr_ioregs,
|
|
&acc_mx6d_grp_ioregs);
|
|
mx6_dram_cfg(&acc_mx6d_ddr_info, &acc_mx6d_mmdc_calib,
|
|
&acc_mx6d_mem_ddr3_1066);
|
|
/* Perform DDR DRAM calibration */
|
|
udelay(100);
|
|
mmdc_do_write_level_calibration(&acc_mx6d_ddr_info);
|
|
mmdc_do_dqs_calibration(&acc_mx6d_ddr_info);
|
|
break;
|
|
}
|
|
}
|
|
|
|
void board_init_f(ulong dummy)
|
|
{
|
|
/* setup AIPS and disable watchdog power-down counter (only enabled after reset) */
|
|
arch_cpu_init();
|
|
|
|
ccgr_init();
|
|
gpr_init();
|
|
|
|
/* setup GP timer */
|
|
timer_init();
|
|
|
|
/* Enable device tree and early DM support*/
|
|
spl_early_init();
|
|
|
|
/* Setup early required pinmuxes */
|
|
setup_iomux_early();
|
|
set_early_gpio();
|
|
|
|
/* Setup UART pinmux */
|
|
setup_iomux_uart();
|
|
|
|
/* UART clocks enabled and gd valid - init serial console */
|
|
preloader_console_init();
|
|
|
|
setup_ddr();
|
|
|
|
/* Clear the BSS. */
|
|
memset(__bss_start, 0, __bss_end - __bss_start);
|
|
|
|
/* load/boot image from boot device */
|
|
board_init_r(NULL, 0);
|
|
}
|
|
#endif
|
|
|
|
#if IS_ENABLED(CONFIG_USB_EHCI_MX6)
|
|
#define USB_OTHERREGS_OFFSET 0x800
|
|
#define UCTRL_PWR_POL BIT(9)
|
|
|
|
int board_usb_phy_mode(int port)
|
|
{
|
|
if (port == 1)
|
|
return USB_INIT_HOST;
|
|
else
|
|
return usb_phy_mode(port);
|
|
}
|
|
|
|
int board_ehci_hcd_init(int port)
|
|
{
|
|
u32 *usbnc_usb_ctrl;
|
|
|
|
if (port > 1)
|
|
return -EINVAL;
|
|
|
|
usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
|
|
port * 4);
|
|
|
|
/* Set Power polarity */
|
|
setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
|
|
|
|
return 0;
|
|
}
|
|
#endif
|
|
|
|
int board_fit_config_name_match(const char *name)
|
|
{
|
|
if (!strcmp(name, "imx6q-bosch-acc"))
|
|
return 0;
|
|
return -1;
|
|
}
|
|
|
|
void reset_cpu(ulong addr)
|
|
{
|
|
puts("Hanging CPU for watchdog reset!\n");
|
|
hang();
|
|
}
|
|
|
|
#if CONFIG_IS_ENABLED(SHOW_BOOT_PROGRESS)
|
|
void show_boot_progress(int val)
|
|
{
|
|
u32 fuseval;
|
|
int ret;
|
|
|
|
if (val < 0)
|
|
val *= -1;
|
|
|
|
switch (val) {
|
|
case BOOTSTAGE_ID_ENTER_CLI_LOOP:
|
|
printf("autoboot failed, check fuse\n");
|
|
ret = fuse_read(0, 6, &fuseval);
|
|
if (ret == 0 && (fuseval & 0x2) == 0x0) {
|
|
printf("Enter cmdline, as device not closed\n");
|
|
return;
|
|
}
|
|
ret = fuse_read(5, 7, &fuseval);
|
|
if (ret == 0 && fuseval == 0x0) {
|
|
printf("Enter cmdline, as it is a Development device\n");
|
|
return;
|
|
}
|
|
panic("do not enter cmdline");
|
|
break;
|
|
}
|
|
}
|
|
#endif
|