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9539738509
Now that we have a 'positive' Kconfig option, use this instead of the negative one, which is harder to understand. Signed-off-by: Simon Glass <sjg@chromium.org>
255 lines
6.5 KiB
C
255 lines
6.5 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2019 Rockchip Electronics Co., Ltd
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*/
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#include <common.h>
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#include <dm.h>
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#include <log.h>
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#include <dm/pinctrl.h>
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#include <regmap.h>
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#include <linux/bitops.h>
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#include "pinctrl-rockchip.h"
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static struct rockchip_mux_route_data rk3288_mux_route_data[] = {
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{
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/* edphdmi_cecinoutt1 */
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.bank_num = 7,
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.pin = 16,
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.func = 2,
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.route_offset = 0x264,
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.route_val = BIT(16 + 12) | BIT(12),
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}, {
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/* edphdmi_cecinout */
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.bank_num = 7,
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.pin = 23,
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.func = 4,
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.route_offset = 0x264,
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.route_val = BIT(16 + 12),
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},
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};
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static int rk3288_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
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{
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struct rockchip_pinctrl_priv *priv = bank->priv;
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int iomux_num = (pin / 8);
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struct regmap *regmap;
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int reg, ret, mask, mux_type;
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u8 bit;
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u32 data, route_reg, route_val;
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regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
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? priv->regmap_pmu : priv->regmap_base;
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/* get basic quadrupel of mux registers and the correct reg inside */
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mux_type = bank->iomux[iomux_num].type;
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reg = bank->iomux[iomux_num].offset;
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reg += rockchip_get_mux_data(mux_type, pin, &bit, &mask);
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if (bank->route_mask & BIT(pin)) {
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if (rockchip_get_mux_route(bank, pin, mux, &route_reg,
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&route_val)) {
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ret = regmap_write(regmap, route_reg, route_val);
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if (ret)
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return ret;
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}
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}
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/* bank0 is special, there are no higher 16 bit writing bits. */
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if (bank->bank_num == 0) {
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regmap_read(regmap, reg, &data);
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data &= ~(mask << bit);
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} else {
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/* enable the write to the equivalent lower bits */
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data = (mask << (bit + 16));
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}
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data |= (mux & mask) << bit;
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ret = regmap_write(regmap, reg, data);
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return ret;
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}
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#define RK3288_PULL_OFFSET 0x140
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#define RK3288_PULL_PMU_OFFSET 0x64
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static void rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
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int pin_num, struct regmap **regmap,
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int *reg, u8 *bit)
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{
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struct rockchip_pinctrl_priv *priv = bank->priv;
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/* The first 24 pins of the first bank are located in PMU */
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if (bank->bank_num == 0) {
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*regmap = priv->regmap_pmu;
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*reg = RK3288_PULL_PMU_OFFSET;
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} else {
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*regmap = priv->regmap_base;
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*reg = RK3288_PULL_OFFSET;
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/* correct the offset, as we're starting with the 2nd bank */
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*reg -= 0x10;
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*reg += bank->bank_num * ROCKCHIP_PULL_BANK_STRIDE;
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}
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*reg += ((pin_num / ROCKCHIP_PULL_PINS_PER_REG) * 4);
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*bit = (pin_num % ROCKCHIP_PULL_PINS_PER_REG);
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*bit *= ROCKCHIP_PULL_BITS_PER_PIN;
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}
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static int rk3288_set_pull(struct rockchip_pin_bank *bank,
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int pin_num, int pull)
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{
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struct regmap *regmap;
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int reg, ret;
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u8 bit, type;
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u32 data;
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if (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT)
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return -ENOTSUPP;
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rk3288_calc_pull_reg_and_bit(bank, pin_num, ®map, ®, &bit);
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type = bank->pull_type[pin_num / 8];
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ret = rockchip_translate_pull_value(type, pull);
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if (ret < 0) {
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debug("unsupported pull setting %d\n", pull);
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return ret;
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}
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/* bank0 is special, there are no higher 16 bit writing bits */
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if (bank->bank_num == 0) {
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regmap_read(regmap, reg, &data);
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data &= ~(((1 << ROCKCHIP_PULL_BITS_PER_PIN) - 1) << bit);
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} else {
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/* enable the write to the equivalent lower bits */
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data = ((1 << ROCKCHIP_PULL_BITS_PER_PIN) - 1) << (bit + 16);
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}
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data |= (ret << bit);
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ret = regmap_write(regmap, reg, data);
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return ret;
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}
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#define RK3288_DRV_PMU_OFFSET 0x70
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#define RK3288_DRV_GRF_OFFSET 0x1c0
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static void rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
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int pin_num, struct regmap **regmap,
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int *reg, u8 *bit)
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{
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struct rockchip_pinctrl_priv *priv = bank->priv;
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/* The first 24 pins of the first bank are located in PMU */
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if (bank->bank_num == 0) {
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*regmap = priv->regmap_pmu;
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*reg = RK3288_DRV_PMU_OFFSET;
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} else {
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*regmap = priv->regmap_base;
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*reg = RK3288_DRV_GRF_OFFSET;
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/* correct the offset, as we're starting with the 2nd bank */
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*reg -= 0x10;
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*reg += bank->bank_num * ROCKCHIP_DRV_BANK_STRIDE;
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}
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*reg += ((pin_num / ROCKCHIP_DRV_PINS_PER_REG) * 4);
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*bit = (pin_num % ROCKCHIP_DRV_PINS_PER_REG);
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*bit *= ROCKCHIP_DRV_BITS_PER_PIN;
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}
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static int rk3288_set_drive(struct rockchip_pin_bank *bank,
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int pin_num, int strength)
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{
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struct regmap *regmap;
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int reg, ret;
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u32 data;
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u8 bit;
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int type = bank->drv[pin_num / 8].drv_type;
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rk3288_calc_drv_reg_and_bit(bank, pin_num, ®map, ®, &bit);
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ret = rockchip_translate_drive_value(type, strength);
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if (ret < 0) {
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debug("unsupported driver strength %d\n", strength);
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return ret;
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}
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/* bank0 is special, there are no higher 16 bit writing bits. */
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if (bank->bank_num == 0) {
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regmap_read(regmap, reg, &data);
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data &= ~(((1 << ROCKCHIP_DRV_BITS_PER_PIN) - 1) << bit);
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} else {
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/* enable the write to the equivalent lower bits */
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data = ((1 << ROCKCHIP_DRV_BITS_PER_PIN) - 1) << (bit + 16);
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}
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data |= (ret << bit);
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ret = regmap_write(regmap, reg, data);
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return ret;
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}
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static struct rockchip_pin_bank rk3288_pin_banks[] = {
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PIN_BANK_IOMUX_FLAGS(0, 24, "gpio0", IOMUX_SOURCE_PMU,
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IOMUX_SOURCE_PMU,
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IOMUX_SOURCE_PMU,
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IOMUX_UNROUTED
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),
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PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_UNROUTED,
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IOMUX_UNROUTED,
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IOMUX_UNROUTED,
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0
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),
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PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, IOMUX_UNROUTED),
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PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, IOMUX_WIDTH_4BIT),
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PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT,
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IOMUX_WIDTH_4BIT,
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0,
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0
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),
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PIN_BANK_IOMUX_FLAGS(5, 32, "gpio5", IOMUX_UNROUTED,
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0,
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0,
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IOMUX_UNROUTED
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),
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PIN_BANK_IOMUX_FLAGS(6, 32, "gpio6", 0, 0, 0, IOMUX_UNROUTED),
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PIN_BANK_IOMUX_FLAGS(7, 32, "gpio7", 0,
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0,
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IOMUX_WIDTH_4BIT,
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IOMUX_UNROUTED
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),
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PIN_BANK(8, 16, "gpio8"),
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};
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static struct rockchip_pin_ctrl rk3288_pin_ctrl = {
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.pin_banks = rk3288_pin_banks,
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.nr_banks = ARRAY_SIZE(rk3288_pin_banks),
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.grf_mux_offset = 0x0,
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.pmu_mux_offset = 0x84,
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.iomux_routes = rk3288_mux_route_data,
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.niomux_routes = ARRAY_SIZE(rk3288_mux_route_data),
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.set_mux = rk3288_set_mux,
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.set_pull = rk3288_set_pull,
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.set_drive = rk3288_set_drive,
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};
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static const struct udevice_id rk3288_pinctrl_ids[] = {
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{
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.compatible = "rockchip,rk3288-pinctrl",
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.data = (ulong)&rk3288_pin_ctrl
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},
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{ }
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};
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U_BOOT_DRIVER(rockchip_rk3288_pinctrl) = {
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.name = "rockchip_rk3288_pinctrl",
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.id = UCLASS_PINCTRL,
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.of_match = rk3288_pinctrl_ids,
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.priv_auto = sizeof(struct rockchip_pinctrl_priv),
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.ops = &rockchip_pinctrl_ops,
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#if CONFIG_IS_ENABLED(OF_REAL)
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.bind = dm_scan_fdt_dev,
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#endif
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.probe = rockchip_pinctrl_probe,
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};
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