mirror of
https://github.com/AsahiLinux/u-boot
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9376d799de
Sync with the latest DDR initialization from Phytec, which uses version 1.2 of NXP's i.MX7D DRAM Register Programming Aid spreadsheet. This updated DDR initialization fixes occasional system freeze. Signed-off-by: Fabio Estevam <festevam@denx.de>
123 lines
3 KiB
INI
123 lines
3 KiB
INI
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2017 PHYTEC America, LLC
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*
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* Refer doc/imx/mkimage/imximage.txt for more details about how-to configure
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* and create imximage boot image
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*
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* The syntax is taken as close as possible with the kwbimage
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*/
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#define __ASSEMBLY__
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#include <config.h>
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IMAGE_VERSION 2
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#ifdef CONFIG_IMX_HAB
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CSF CONFIG_CSF_SIZE
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#endif
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BOOT_FROM sd
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/*
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* Device Configuration Data (DCD)
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*
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* Each entry must have the format:
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* Addr-type Address Value
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*
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* where:
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* Addr-type register length (1,2 or 4 bytes)
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* Address absolute address of the register
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* value value to be stored in the register
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*/
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/*
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* Device Configuration Data (DCD)
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*
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* Each entry must have the format:
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* Addr-type Address Value
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*
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* where:
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* Addr-type register length (1,2 or 4 bytes)
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* Address absolute address of the register
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* value value to be stored in the register
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*/
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/* DDR initialization came from Phytec */
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DATA 4 0x30340004 0x4F400005
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/* Clear then set bit30 to ensure exit from DDR retention */
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DATA 4 0x30360388 0x40000000
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DATA 4 0x30360384 0x40000000
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/* deassert presetn */
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DATA 4 0x30391000 0x00000002
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/* DDR Controller Regs */
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DATA 4 0x307a0000 0x01040001
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DATA 4 0x307a0064 0x00400046
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DATA 4 0x307a0490 0x00000001
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DATA 4 0x307a00d4 0x00690000
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DATA 4 0x307a00d0 0x00020083
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DATA 4 0x307a00dc 0x09300004
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DATA 4 0x307a00e0 0x04480000
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DATA 4 0x307a00e4 0x00100004
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DATA 4 0x307a00f4 0x0000033f
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DATA 4 0x307a0100 0x090e110a
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DATA 4 0x307a0104 0x0007020e
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DATA 4 0x307a0108 0x03040407
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DATA 4 0x307a010c 0x00002006
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DATA 4 0x307a0110 0x04020304
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DATA 4 0x307a0114 0x03030202
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DATA 4 0x307a0120 0x00000803
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DATA 4 0x307a0180 0x00800020
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DATA 4 0x307a0190 0x02098204
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DATA 4 0x307a0194 0x00030303
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DATA 4 0x307a01a0 0x80400003
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DATA 4 0x307a01a4 0x00100020
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DATA 4 0x307a01a8 0x80100004
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DATA 4 0x307a0200 0x0000001f
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DATA 4 0x307a0204 0x00080808
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DATA 4 0x307a020c 0x00000000
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DATA 4 0x307a0210 0x00000f0f
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DATA 4 0x307a0214 0x07070707
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DATA 4 0x307a0218 0x0f070707
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DATA 4 0x307a0240 0x06000604
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DATA 4 0x307a0244 0x00000001
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/* deassert presetn */
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DATA 4 0x30391000 0x00000000
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/* PHY Controller Regs */
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DATA 4 0x30790000 0x17420f40
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DATA 4 0x30790004 0x10210100
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DATA 4 0x30790010 0x00060807
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DATA 4 0x307900b0 0x1010007e
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DATA 4 0x3079009c 0x00000d6e
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/* write leveling values for each byte lane */
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DATA 4 0x3079006c 0x06090108
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/* write leveling resync cycle */
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DATA 4 0x30790078 0x00000001
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DATA 4 0x30790078 0x00000000
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DATA 4 0x30790030 0x08080808
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DATA 4 0x30790020 0x08080808
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DATA 4 0x30790050 0x01000010
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DATA 4 0x30790050 0x00000010
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DATA 4 0x30790018 0x0000000f
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/* start manual ZQ */
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DATA 4 0x307900c0 0x0e407304
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DATA 4 0x307900c0 0x0e447304
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DATA 4 0x307900c0 0x0e447306
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DATA 4 0x307900c0 0x0e447304
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CHECK_BITS_SET 4 0x307900c4 0x1
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/* end manual ZQ */
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DATA 4 0x307900c0 0x0e407304
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/* final init sequence */
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DATA 4 0x30384130 0x00000000
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DATA 4 0x30340020 0x00000178
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DATA 4 0x30384130 0x00000002
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DATA 4 0x30790018 0x0000000f
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CHECK_BITS_SET 4 0x307a0004 0x1
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