mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-26 13:03:40 +00:00
83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
383 lines
9.1 KiB
C
383 lines
9.1 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2017 DENX Software Engineering
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* Lukasz Majewski, DENX Software Engineering, lukma@denx.de
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*/
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#include <common.h>
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#include <dm.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/iomux.h>
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#include <asm/arch/mx6-pins.h>
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#include <asm/arch/mx6-ddr.h>
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#include <asm/arch/sys_proto.h>
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#include <errno.h>
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#include <asm/gpio.h>
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#include <malloc.h>
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#include <asm/mach-imx/iomux-v3.h>
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#include <asm/mach-imx/mxc_i2c.h>
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#include <asm/mach-imx/boot_mode.h>
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#include <asm/mach-imx/spi.h>
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#include <mmc.h>
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#include <fsl_esdhc.h>
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#include <miiphy.h>
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#include <netdev.h>
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#include <i2c.h>
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#include <dm.h>
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#include <dm/platform_data/serial_mxc.h>
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#include <dm/platdata.h>
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#ifndef CONFIG_MXC_SPI
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#error "CONFIG_SPI must be set for this board"
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#error "Please check your config file"
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#endif
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#include "common.h"
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DECLARE_GLOBAL_DATA_PTR;
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static bool hw_ids_valid;
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static bool sw_ids_valid;
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static u32 cpu_id;
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static u32 unit_id;
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#define SW0 IMX_GPIO_NR(2, 4)
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#define SW1 IMX_GPIO_NR(2, 5)
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#define SW2 IMX_GPIO_NR(2, 6)
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#define SW3 IMX_GPIO_NR(2, 7)
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#define HW0 IMX_GPIO_NR(6, 7)
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#define HW1 IMX_GPIO_NR(6, 9)
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#define HW2 IMX_GPIO_NR(6, 10)
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#define HW3 IMX_GPIO_NR(6, 11)
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#define HW4 IMX_GPIO_NR(4, 7)
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#define HW5 IMX_GPIO_NR(4, 11)
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#define HW6 IMX_GPIO_NR(4, 13)
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#define HW7 IMX_GPIO_NR(4, 15)
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int gpio_table_sw_ids[] = {
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SW0, SW1, SW2, SW3
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};
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const char *gpio_table_sw_ids_names[] = {
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"sw0", "sw1", "sw2", "sw3"
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};
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int gpio_table_hw_ids[] = {
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HW0, HW1, HW2, HW3, HW4, HW5, HW6, HW7
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};
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const char *gpio_table_hw_ids_names[] = {
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"hw0", "hw1", "hw2", "hw3", "hw4", "hw5", "hw6", "hw7"
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};
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static int get_board_id(int *ids, const char **c, int size,
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bool *valid, u32 *id)
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{
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int i, ret, val;
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*valid = false;
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for (i = 0; i < size; i++) {
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ret = gpio_request(ids[i], c[i]);
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if (ret) {
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printf("Can't request SWx gpios\n");
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return ret;
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}
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}
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for (i = 0; i < size; i++) {
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ret = gpio_direction_input(ids[i]);
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if (ret) {
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printf("Can't set SWx gpios direction\n");
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return ret;
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}
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}
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for (i = 0; i < size; i++) {
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val = gpio_get_value(ids[i]);
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if (val < 0) {
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printf("Can't get SW%d ID\n", i);
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*id = 0;
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return val;
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}
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*id |= val << i;
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}
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*valid = true;
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return 0;
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}
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int dram_init(void)
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{
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gd->ram_size = imx_ddr_size();
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return 0;
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}
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#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
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/* I2C1: TFA9879 */
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struct i2c_pads_info i2c_pad_info0 = {
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.scl = {
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.i2c_mode = MX6_PAD_EIM_D21__I2C1_SCL | PC,
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.gpio_mode = MX6_PAD_EIM_D21__GPIO3_IO21 | PC,
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.gp = IMX_GPIO_NR(3, 21)
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},
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.sda = {
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.i2c_mode = MX6_PAD_EIM_D28__I2C1_SDA | PC,
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.gpio_mode = MX6_PAD_EIM_D28__GPIO3_IO28 | PC,
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.gp = IMX_GPIO_NR(3, 28)
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}
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};
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/* I2C2: TIVO TM4C123 */
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struct i2c_pads_info i2c_pad_info1 = {
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.scl = {
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.i2c_mode = MX6_PAD_EIM_EB2__I2C2_SCL | PC,
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.gpio_mode = MX6_PAD_EIM_EB2__GPIO2_IO30 | PC,
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.gp = IMX_GPIO_NR(2, 30)
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},
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.sda = {
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.i2c_mode = MX6_PAD_EIM_D16__I2C2_SDA | PC,
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.gpio_mode = MX6_PAD_EIM_D16__GPIO3_IO16 | PC,
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.gp = IMX_GPIO_NR(3, 16)
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}
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};
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/* I2C3: PMIC PF0100, EEPROM AT24C256C */
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struct i2c_pads_info i2c_pad_info2 = {
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.scl = {
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.i2c_mode = MX6_PAD_EIM_D17__I2C3_SCL | PC,
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.gpio_mode = MX6_PAD_EIM_D17__GPIO3_IO17 | PC,
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.gp = IMX_GPIO_NR(3, 17)
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},
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.sda = {
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.i2c_mode = MX6_PAD_EIM_D18__I2C3_SDA | PC,
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.gpio_mode = MX6_PAD_EIM_D18__GPIO3_IO18 | PC,
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.gp = IMX_GPIO_NR(3, 18)
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}
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};
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iomux_v3_cfg_t const misc_pads[] = {
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/* Prod ID GPIO pins */
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MX6_PAD_NANDF_D4__GPIO2_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL),
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MX6_PAD_NANDF_D5__GPIO2_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL),
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MX6_PAD_NANDF_D6__GPIO2_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL),
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MX6_PAD_NANDF_D7__GPIO2_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL),
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/* HW revision GPIO pins */
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MX6_PAD_NANDF_CLE__GPIO6_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL),
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MX6_PAD_NANDF_WP_B__GPIO6_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL),
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MX6_PAD_NANDF_RB0__GPIO6_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
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MX6_PAD_NANDF_CS0__GPIO6_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
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MX6_PAD_KEY_ROW0__GPIO4_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL),
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MX6_PAD_KEY_ROW2__GPIO4_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
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MX6_PAD_KEY_ROW3__GPIO4_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL),
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MX6_PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
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/* XTALOSC */
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MX6_PAD_GPIO_3__XTALOSC_REF_CLK_24M | MUX_PAD_CTRL(NO_PAD_CTRL),
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};
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#ifdef CONFIG_FSL_ESDHC
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struct fsl_esdhc_cfg usdhc_cfg[1] = {
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{ USDHC4_BASE_ADDR, 0, 8, },
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};
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int board_mmc_getcd(struct mmc *mmc)
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{
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return 1;
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}
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int board_mmc_init(bd_t *bis)
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{
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displ5_set_iomux_usdhc();
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usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
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return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
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}
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#endif /* CONFIG_FSL_ESDHC */
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static void displ5_setup_ecspi(void)
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{
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int ret;
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displ5_set_iomux_ecspi();
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ret = gpio_request(IMX_GPIO_NR(5, 29), "spi2_cs0");
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if (!ret)
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gpio_direction_output(IMX_GPIO_NR(5, 29), 1);
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ret = gpio_request(IMX_GPIO_NR(7, 0), "spi2_#wp");
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if (!ret)
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gpio_direction_output(IMX_GPIO_NR(7, 0), 1);
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}
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#ifdef CONFIG_FEC_MXC
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iomux_v3_cfg_t const enet_pads[] = {
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MX6_PAD_ENET_TXD1__ENET_1588_EVENT0_IN | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_ENET_RXD1__ENET_1588_EVENT3_OUT | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
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/* for old evalboard with R159 present and R160 not populated */
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MX6_PAD_GPIO_16__ENET_REF_CLK | MUX_PAD_CTRL(NO_PAD_CTRL),
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MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
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/*INT#_GBE*/
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MX6_PAD_ENET_TX_EN__GPIO1_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL),
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};
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static void setup_iomux_enet(void)
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{
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SETUP_IOMUX_PADS(enet_pads);
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gpio_direction_input(IMX_GPIO_NR(1, 28)); /*INT#_GBE*/
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}
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int board_eth_init(bd_t *bd)
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{
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struct phy_device *phydev;
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struct mii_dev *bus;
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int ret;
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setup_iomux_enet();
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iomuxc_set_rgmii_io_voltage(DDR_SEL_1P5V_IO);
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ret = enable_fec_anatop_clock(0, ENET_125MHZ);
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if (ret)
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return ret;
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bus = fec_get_miibus(IMX_FEC_BASE, -1);
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if (!bus)
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return -ENODEV;
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/*
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* We use here the "rgmii-id" mode of operation and allow M88E1512
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* PHY to use its internally callibrated RX/TX delays
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*/
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phydev = phy_find_by_mask(bus, 0xffffffff /* (0xf << 4) */,
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PHY_INTERFACE_MODE_RGMII_ID);
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if (!phydev) {
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ret = -ENODEV;
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goto err_phy;
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}
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/* display5 due to PCB routing can only work with 100 Mbps */
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phydev->advertising &= ~(ADVERTISED_1000baseX_Half |
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ADVERTISED_1000baseX_Full |
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SUPPORTED_1000baseT_Half |
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SUPPORTED_1000baseT_Full);
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ret = fec_probe(bd, -1, IMX_FEC_BASE, bus, phydev);
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if (ret)
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goto err_sw;
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return 0;
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err_sw:
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free(phydev);
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err_phy:
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mdio_unregister(bus);
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free(bus);
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return ret;
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}
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#endif /* CONFIG_FEC_MXC */
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/*
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* Do not overwrite the console
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* Always use serial for U-Boot console
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*/
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int overwrite_console(void)
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{
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return 1;
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}
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#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
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int ft_board_setup(void *blob, bd_t *bd)
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{
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fdt_fixup_ethernet(blob);
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return 0;
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}
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#endif
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int board_init(void)
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{
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debug("board init\n");
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/* address of boot parameters */
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gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
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/* Setup iomux for non console UARTS */
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displ5_set_iomux_uart();
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displ5_setup_ecspi();
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SETUP_IOMUX_PADS(misc_pads);
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get_board_id(gpio_table_sw_ids, &gpio_table_sw_ids_names[0],
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ARRAY_SIZE(gpio_table_sw_ids), &sw_ids_valid, &unit_id);
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debug("SWx unit_id 0x%x\n", unit_id);
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get_board_id(gpio_table_hw_ids, &gpio_table_hw_ids_names[0],
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ARRAY_SIZE(gpio_table_hw_ids), &hw_ids_valid, &cpu_id);
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debug("HWx cpu_id 0x%x\n", cpu_id);
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if (hw_ids_valid && sw_ids_valid)
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printf("ID: unit type 0x%x rev 0x%x\n", unit_id, cpu_id);
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udelay(25);
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setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0);
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setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
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setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
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return 0;
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}
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#ifdef CONFIG_CMD_BMODE
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static const struct boot_mode board_boot_modes[] = {
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/* eMMC, USDHC-4, 8-bit bus width */
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/* SPI-NOR, ECSPI-2 SS0, 3-bytes addressing */
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{"emmc", MAKE_CFGVAL(0x60, 0x58, 0x00, 0x00)},
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{"spinor", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x09)},
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{NULL, 0},
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};
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static void setup_boot_modes(void)
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{
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add_board_boot_modes(board_boot_modes);
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}
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#else
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static inline void setup_boot_modes(void) {}
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#endif
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int misc_init_r(void)
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{
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setup_boot_modes();
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return 0;
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}
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static struct mxc_serial_platdata mxc_serial_plat = {
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.reg = (struct mxc_uart *)UART5_BASE,
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};
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U_BOOT_DEVICE(mxc_serial) = {
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.name = "serial_mxc",
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.platdata = &mxc_serial_plat,
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};
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