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6806a133cd
The intention of change_k0_cca() is to read the C0.Config register into
register $t0, update $t0 with the new cache coherency mode passed in $a0
and write back $t0 to C0.Config. With MIPS32 R2 or later instruction
sets, this can be achieved with a single instruction with INS. The
source and destination register of the INS instruction is passed as
first parameter. In case of change_k0_cca() it is register $t0. But
for writing back the updated value to C0.Config, the incorrect $a0
register is used. This is only correct in the MIPS32 R1 code path.
Fix the `mtc0` instruction to write back the value of the $t0 register.
Fix the MIPS32 R1 code path to also store the updated value in $t0.
Reported by user ddqxy138 on Github.
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| .. | ||
| ashldi3.c | ||
| ashrdi3.c | ||
| asm-offsets.c | ||
| boot.c | ||
| bootm.c | ||
| cache.c | ||
| cache_init.S | ||
| genex.S | ||
| libgcc.h | ||
| lshrdi3.c | ||
| Makefile | ||
| reloc.c | ||
| spl.c | ||
| stack.c | ||
| traps.c | ||
| udivdi3.c | ||