mirror of
https://github.com/AsahiLinux/u-boot
synced 2025-02-26 04:17:09 +00:00
db04ff42c7
The help for CONFIG_MTD explains that it needs to be enabled for various things like NAND, etc to be available. It however then doesn't enforce this dependency and so if you have none of these systems present you still need to disable a number of options. Fix this by making places that select/imply one type of flash, but did not do the same, also do this for "MTD". Make boards which hadn't been enabling MTD already but need it now, do so. In a few places, disable CONFIG_CMD_MTDPARTS as it wasn't previously enabled but was now being implied. Signed-off-by: Tom Rini <trini@konsulko.com>
592 lines
15 KiB
Text
592 lines
15 KiB
Text
menu "MIPS architecture"
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depends on MIPS
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config SYS_ARCH
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default "mips"
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config SYS_CPU
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default "mips32" if CPU_MIPS32
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default "mips64" if CPU_MIPS64
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choice
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prompt "Target select"
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optional
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config TARGET_MALTA
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bool "Support malta"
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select HAS_FIXED_TIMER_FREQUENCY
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select BOARD_EARLY_INIT_R
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select DM
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select DM_SERIAL
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select PCI
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select DYNAMIC_IO_PORT_BASE
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select MIPS_CM
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select MIPS_INSERT_BOOT_CONFIG
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select SYS_CACHE_SHIFT_6
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select MIPS_L2_CACHE
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select OF_CONTROL
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select OF_ISA_BUS
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select PCI_MAP_SYSTEM_MEMORY
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select ROM_EXCEPTION_VECTORS
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select SUPPORTS_BIG_ENDIAN
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select SUPPORTS_CPU_MIPS32_R1
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select SUPPORTS_CPU_MIPS32_R2
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select SUPPORTS_CPU_MIPS32_R6
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select SUPPORTS_CPU_MIPS64_R1
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select SUPPORTS_CPU_MIPS64_R2
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select SUPPORTS_CPU_MIPS64_R6
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select SUPPORTS_LITTLE_ENDIAN
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select SWAP_IO_SPACE
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imply CMD_DM
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config ARCH_ATH79
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bool "Support QCA/Atheros ath79"
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select HAS_FIXED_TIMER_FREQUENCY
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select DM
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select OF_CONTROL
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imply CMD_DM
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config ARCH_MSCC
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bool "Support MSCC VCore-III"
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select HAS_FIXED_TIMER_FREQUENCY
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select OF_CONTROL
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select DM
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config ARCH_BMIPS
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bool "Support BMIPS SoCs"
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select HAS_FIXED_TIMER_FREQUENCY
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select CLK
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select CPU
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select DM
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select OF_CONTROL
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select RAM
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select SYSRESET
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imply CMD_DM
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config ARCH_MTMIPS
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bool "Support MediaTek MIPS platforms"
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select HAS_FIXED_TIMER_FREQUENCY
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select CLK
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imply CMD_DM
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select DISPLAY_CPUINFO
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select DM
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imply DM_GPIO
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select DM_RESET
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select DM_SERIAL
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select PINCTRL
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select PINMUX
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select PINCONF
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select RESET_MTMIPS
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imply MTD
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imply DM_SPI
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imply DM_SPI_FLASH
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select LAST_STAGE_INIT
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select MIPS_TUNE_24KC
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select OF_CONTROL
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select ROM_EXCEPTION_VECTORS
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select SUPPORTS_CPU_MIPS32_R1
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select SUPPORTS_CPU_MIPS32_R2
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select SUPPORTS_LITTLE_ENDIAN
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select SUPPORT_SPL
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config ARCH_JZ47XX
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bool "Support Ingenic JZ47xx"
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select SUPPORT_SPL
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select HAS_FIXED_TIMER_FREQUENCY
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select OF_CONTROL
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select DM
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config ARCH_OCTEON
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bool "Support Marvell Octeon CN7xxx platforms"
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select ARCH_EARLY_INIT_R
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select CPU_CAVIUM_OCTEON
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select DISPLAY_CPUINFO
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select DMA_ADDR_T_64BIT
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select DM
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select DM_GPIO
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select DM_I2C
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select DM_SERIAL
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select DM_SPI
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select MIPS_L2_CACHE
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select MIPS_MACH_EARLY_INIT
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select MIPS_TUNE_OCTEON3
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select MTD
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select ROM_EXCEPTION_VECTORS
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select SUPPORTS_BIG_ENDIAN
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select SUPPORTS_CPU_MIPS64_OCTEON
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select PHYS_64BIT
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select OF_CONTROL
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select OF_LIVE
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imply CMD_DM
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config MACH_PIC32
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bool "Support Microchip PIC32"
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select HAS_FIXED_TIMER_FREQUENCY
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select DM
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select DM_EVENT
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select OF_CONTROL
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imply CMD_DM
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config TARGET_BOSTON
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bool "Support Boston"
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select HAS_FIXED_TIMER_FREQUENCY
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select DM
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select DM_SERIAL
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select MIPS_CM
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select SYS_CACHE_SHIFT_6
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select MIPS_L2_CACHE
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select OF_BOARD_SETUP
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select OF_CONTROL
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select ROM_EXCEPTION_VECTORS
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select SUPPORTS_BIG_ENDIAN
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select SUPPORTS_CPU_MIPS32_R1
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select SUPPORTS_CPU_MIPS32_R2
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select SUPPORTS_CPU_MIPS32_R6
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select SUPPORTS_CPU_MIPS64_R1
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select SUPPORTS_CPU_MIPS64_R2
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select SUPPORTS_CPU_MIPS64_R6
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select SUPPORTS_LITTLE_ENDIAN
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imply CMD_DM
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config TARGET_XILFPGA
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bool "Support Imagination Xilfpga"
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select HAS_FIXED_TIMER_FREQUENCY
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select DM
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select DM_GPIO
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select DM_SERIAL
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select SYS_CACHE_SHIFT_4
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select OF_CONTROL
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select ROM_EXCEPTION_VECTORS
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select SUPPORTS_CPU_MIPS32_R1
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select SUPPORTS_CPU_MIPS32_R2
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select SUPPORTS_LITTLE_ENDIAN
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imply CMD_DM
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help
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This supports IMGTEC MIPSfpga platform
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endchoice
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source "board/imgtec/boston/Kconfig"
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source "board/imgtec/malta/Kconfig"
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source "board/imgtec/xilfpga/Kconfig"
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source "arch/mips/mach-ath79/Kconfig"
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source "arch/mips/mach-mscc/Kconfig"
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source "arch/mips/mach-bmips/Kconfig"
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source "arch/mips/mach-jz47xx/Kconfig"
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source "arch/mips/mach-pic32/Kconfig"
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source "arch/mips/mach-mtmips/Kconfig"
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source "arch/mips/mach-octeon/Kconfig"
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if MIPS
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choice
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prompt "CPU selection"
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default CPU_MIPS32_R2
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config CPU_MIPS32_R1
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bool "MIPS32 Release 1"
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depends on SUPPORTS_CPU_MIPS32_R1
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select 32BIT
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help
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Choose this option to build an U-Boot for release 1 through 5 of the
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MIPS32 architecture.
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config CPU_MIPS32_R2
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bool "MIPS32 Release 2"
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depends on SUPPORTS_CPU_MIPS32_R2
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select 32BIT
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help
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Choose this option to build an U-Boot for release 2 through 5 of the
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MIPS32 architecture.
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config CPU_MIPS32_R6
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bool "MIPS32 Release 6"
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depends on SUPPORTS_CPU_MIPS32_R6
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select 32BIT
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help
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Choose this option to build an U-Boot for release 6 or later of the
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MIPS32 architecture.
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config CPU_MIPS64_R1
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bool "MIPS64 Release 1"
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depends on SUPPORTS_CPU_MIPS64_R1
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select 64BIT
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help
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Choose this option to build a kernel for release 1 through 5 of the
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MIPS64 architecture.
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config CPU_MIPS64_R2
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bool "MIPS64 Release 2"
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depends on SUPPORTS_CPU_MIPS64_R2
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select 64BIT
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help
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Choose this option to build a kernel for release 2 through 5 of the
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MIPS64 architecture.
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config CPU_MIPS64_R6
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bool "MIPS64 Release 6"
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depends on SUPPORTS_CPU_MIPS64_R6
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select 64BIT
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help
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Choose this option to build a kernel for release 6 or later of the
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MIPS64 architecture.
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config CPU_MIPS64_OCTEON
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bool "Marvell Octeon series of CPUs"
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depends on SUPPORTS_CPU_MIPS64_OCTEON
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select 64BIT
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help
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Choose this option for Marvell Octeon CPUs. These CPUs are between
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MIPS64 R5 and R6 with other extensions.
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endchoice
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menu "General setup"
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config ROM_EXCEPTION_VECTORS
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bool "Build U-Boot image with exception vectors"
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help
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Enable this to include exception vectors in the U-Boot image. This is
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required if the U-Boot entry point is equal to the address of the
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CPU reset exception vector (e.g. U-Boot as ROM loader in Qemu,
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U-Boot booted from parallel NOR flash).
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Disable this, if the U-Boot image is booted from DRAM (e.g. by SPL).
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In that case the image size will be reduced by 0x500 bytes.
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config SYS_MIPS_TIMER_FREQ
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int "Fixed MIPS CPU timer frequency in Hz"
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depends on HAS_FIXED_TIMER_FREQUENCY
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help
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Configures a fixed CPU timer frequency.
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config MIPS_CM_BASE
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hex "MIPS CM GCR Base Address"
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depends on MIPS_CM
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default 0x16100000 if TARGET_BOSTON
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default 0x1fbf8000
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help
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The physical base address at which to map the MIPS Coherence Manager
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Global Configuration Registers (GCRs). This should be set such that
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the GCRs occupy a region of the physical address space which is
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otherwise unused, or at minimum that software doesn't need to access.
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config MIPS_CACHE_INDEX_BASE
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hex "Index base address for cache initialisation"
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default 0x80000000 if CPU_MIPS32
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default 0xffffffff80000000 if CPU_MIPS64
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help
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This is the base address for a memory block, which is used for
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initialising the cache lines. This is also the base address of a memory
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block which is used for loading and filling cache lines when
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SYS_MIPS_CACHE_INIT_RAM_LOAD is selected.
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Normally this is CKSEG0. If the MIPS system needs to move this block
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to some SRAM or ScratchPad RAM, adapt this option accordingly.
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config MIPS_MACH_EARLY_INIT
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bool "Enable mach specific very early init code"
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help
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Use this to enable the call to mips_mach_early_init() very early
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from start.S. This function can be used e.g. to do some very early
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CPU / SoC intitialization or image copying. Its called very early
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and at this stage the PC might not match the linking address
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(CONFIG_TEXT_BASE) - no absolute jump done until this call.
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config MIPS_CACHE_SETUP
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bool "Allow generic start code to initialize and setup caches"
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default n if SKIP_LOWLEVEL_INIT
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default y
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help
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This allows the generic start code to invoke the generic initialization
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of the CPU caches. Disabling this can be useful for RAM boot scenarios
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(EJTAG, SPL payload) or for machines which don't need cache initialization
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or which want to provide their own cache implementation.
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If unsure, say yes.
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config MIPS_CACHE_DISABLE
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bool "Allow generic start code to initially disable caches"
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default n if SKIP_LOWLEVEL_INIT
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default y
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help
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This allows the generic start code to initially disable the CPU caches
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and run uncached until the caches are initialized and enabled. Disabling
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this can be useful on machines which don't need cache initialization or
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which want to provide their own cache implementation.
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If unsure, say yes.
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config MIPS_RELOCATION_TABLE_SIZE
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hex "Relocation table size"
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range 0x100 0x10000
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default "0x8000"
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---help---
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A table of relocation data will be appended to the U-Boot binary
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and parsed in relocate_code() to fix up all offsets in the relocated
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U-Boot.
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This option allows the amount of space reserved for the table to be
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adjusted in a range from 256 up to 64k. The default is 32k and should
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be ok in most cases. Reduce this value to shrink the size of U-Boot
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binary.
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The build will fail and a valid size suggested if this is too small.
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If unsure, leave at the default value.
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config RESTORE_EXCEPTION_VECTOR_BASE
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bool "Restore exception vector base before booting linux kernel"
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help
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In U-Boot the exception vector base will be moved to top of memory,
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to be used to display register dump when exception occurs.
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But some old linux kernel does not honor the base set in CP0_EBASE.
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A modified exception vector base will cause kernel crash.
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This option will restore the exception vector base to its previous
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value.
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If unsure, say N.
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config OVERRIDE_EXCEPTION_VECTOR_BASE
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bool "Override the exception vector base to be restored"
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depends on RESTORE_EXCEPTION_VECTOR_BASE
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help
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Enable this option if you want to use a different exception vector
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base rather than the previously saved one.
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config NEW_EXCEPTION_VECTOR_BASE
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hex "New exception vector base"
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depends on OVERRIDE_EXCEPTION_VECTOR_BASE
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range 0x80000000 0xbffff000
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default 0x80000000
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help
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The exception vector base to be restored before booting linux kernel
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config INIT_STACK_WITHOUT_MALLOC_F
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bool "Do not reserve malloc space on initial stack"
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help
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Enable this option if you don't want to reserve malloc space on
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initial stack. This is useful if the initial stack can't hold large
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malloc space. Platform should set the malloc_base later when DRAM is
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ready to use.
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config SPL_INIT_STACK_WITHOUT_MALLOC_F
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bool "Do not reserve malloc space on initial stack in SPL"
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help
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Enable this option if you don't want to reserve malloc space on
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initial stack. This is useful if the initial stack can't hold large
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malloc space. Platform should set the malloc_base later when DRAM is
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ready to use.
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config SPL_LOADER_SUPPORT
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bool
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help
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Enable this option if you want to use SPL loaders without DM enabled.
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endmenu
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menu "OS boot interface"
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config MIPS_BOOT_CMDLINE_LEGACY
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bool "Hand over legacy command line to Linux kernel"
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default y
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help
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Enable this option if you want U-Boot to hand over the Yamon-style
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command line to the kernel. All bootargs will be prepared as argc/argv
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compatible list. The argument count (argc) is stored in register $a0.
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The address of the argument list (argv) is stored in register $a1.
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config MIPS_BOOT_ENV_LEGACY
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bool "Hand over legacy environment to Linux kernel"
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default y
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help
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Enable this option if you want U-Boot to hand over the Yamon-style
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environment to the kernel. Information like memory size, initrd
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address and size will be prepared as zero-terminated key/value list.
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The address of the environment is stored in register $a2.
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config MIPS_BOOT_FDT
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bool "Hand over a flattened device tree to Linux kernel"
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help
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Enable this option if you want U-Boot to hand over a flattened
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device tree to the kernel. According to UHI register $a0 will be set
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to -2 and the FDT address is stored in $a1.
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endmenu
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config SUPPORTS_BIG_ENDIAN
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bool
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config SUPPORTS_LITTLE_ENDIAN
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bool
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config SUPPORTS_CPU_MIPS32_R1
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bool
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config SUPPORTS_CPU_MIPS32_R2
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bool
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config SUPPORTS_CPU_MIPS32_R6
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bool
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config SUPPORTS_CPU_MIPS64_R1
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bool
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config SUPPORTS_CPU_MIPS64_R2
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bool
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config SUPPORTS_CPU_MIPS64_R6
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bool
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config SUPPORTS_CPU_MIPS64_OCTEON
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bool
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config HAS_FIXED_TIMER_FREQUENCY
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bool
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config CPU_CAVIUM_OCTEON
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bool
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config CPU_MIPS32
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bool
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default y if CPU_MIPS32_R1 || CPU_MIPS32_R2 || CPU_MIPS32_R6
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config CPU_MIPS64
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bool
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default y if CPU_MIPS64_R1 || CPU_MIPS64_R2 || CPU_MIPS64_R6
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default y if CPU_MIPS64_OCTEON
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config MIPS_TUNE_4KC
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bool
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config MIPS_TUNE_14KC
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bool
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config MIPS_TUNE_24KC
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bool
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config MIPS_TUNE_34KC
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bool
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config MIPS_TUNE_74KC
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bool
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config MIPS_TUNE_OCTEON3
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bool
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config 32BIT
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bool
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config 64BIT
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bool
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config SWAP_IO_SPACE
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bool
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config SYS_MIPS_CACHE_INIT_RAM_LOAD
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bool
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config MIPS_INIT_STACK_IN_SRAM
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bool
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help
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Select this if the initial stack frame could be setup in SRAM.
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Normally the initial stack frame is set up in DRAM which is often
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only available after lowlevel_init. With this option the initial
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stack frame and the early C environment is set up before
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lowlevel_init. Thus lowlevel_init does not need to be implemented
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in assembler.
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config MIPS_SRAM_INIT
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bool
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depends on MIPS_INIT_STACK_IN_SRAM
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help
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Select this if the SRAM for initial stack needs to be initialized
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before it can be used. If enabled, a function mips_sram_init() will
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be called just before setup_stack_gd.
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config DMA_ADDR_T_64BIT
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bool
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help
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Select this to enable 64-bit DMA addressing
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config SYS_DCACHE_SIZE
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int
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default 0
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help
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The total size of the L1 Dcache, if known at compile time.
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config SYS_DCACHE_LINE_SIZE
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int
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default 0
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help
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The size of L1 Dcache lines, if known at compile time.
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config SYS_ICACHE_SIZE
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int
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default 0
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help
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The total size of the L1 ICache, if known at compile time.
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config SYS_ICACHE_LINE_SIZE
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int
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default 0
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help
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The size of L1 Icache lines, if known at compile time.
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config SYS_SCACHE_LINE_SIZE
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|
int
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|
default 0
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help
|
|
The size of L2 cache lines, if known at compile time.
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|
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config SYS_CACHE_SIZE_AUTO
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|
def_bool y if SYS_DCACHE_SIZE = 0 && SYS_ICACHE_SIZE = 0 && \
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SYS_DCACHE_LINE_SIZE = 0 && SYS_ICACHE_LINE_SIZE = 0 && \
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|
SYS_SCACHE_LINE_SIZE = 0
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|
help
|
|
Select this (or let it be auto-selected by not defining any cache
|
|
sizes) in order to allow U-Boot to automatically detect the sizes
|
|
of caches at runtime. This has a small cost in code size & runtime
|
|
so if you know the cache configuration for your system at compile
|
|
time it would be beneficial to configure it.
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|
|
|
config MIPS_L2_CACHE
|
|
bool
|
|
help
|
|
Select this if your system includes an L2 cache and you want U-Boot
|
|
to initialise & maintain it.
|
|
|
|
config DYNAMIC_IO_PORT_BASE
|
|
bool
|
|
|
|
config MIPS_CM
|
|
bool
|
|
help
|
|
Select this if your system contains a MIPS Coherence Manager and you
|
|
wish U-Boot to configure it or make use of it to retrieve system
|
|
information such as cache configuration.
|
|
|
|
config MIPS_INSERT_BOOT_CONFIG
|
|
bool
|
|
help
|
|
Enable this to insert some board-specific boot configuration in
|
|
the U-Boot binary at offset 0x10.
|
|
|
|
config MIPS_BOOT_CONFIG_WORD0
|
|
hex
|
|
depends on MIPS_INSERT_BOOT_CONFIG
|
|
default 0x420 if TARGET_MALTA
|
|
default 0x0
|
|
help
|
|
Value which is inserted as boot config word 0.
|
|
|
|
config MIPS_BOOT_CONFIG_WORD1
|
|
hex
|
|
depends on MIPS_INSERT_BOOT_CONFIG
|
|
default 0x0
|
|
help
|
|
Value which is inserted as boot config word 1.
|
|
|
|
endif
|
|
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|
endmenu
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