mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-12 07:57:21 +00:00
da90d4ce38
Generalized misuse of ble within relocation and bss
initialization loops caused one iteration too many.
Instead of ble ('branch if lower or equal'), use
blo ('branch if lower').
While we're at it, fix all 'addreee' typos.
Signed-off-by: Albert Aribaud <albert.aribaud@free.fr>
705 lines
16 KiB
ArmAsm
705 lines
16 KiB
ArmAsm
/*
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* armboot - Startup Code for XScale
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*
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* Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
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* Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
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* Copyright (C) 2000 Wolfgang Denk <wd@denx.de>
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* Copyright (C) 2001 Alex Zuepke <azu@sysgo.de>
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* Copyright (C) 2002 Kyle Harris <kharris@nexus-tech.net>
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* Copyright (C) 2003 Robert Schwebel <r.schwebel@pengutronix.de>
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* Copyright (C) 2003 Kai-Uwe Bloem <kai-uwe.bloem@auerswald.de>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <config.h>
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#include <version.h>
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#include <asm/arch/pxa-regs.h>
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.globl _start
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_start: b reset
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#ifdef CONFIG_PRELOADER
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ldr pc, _hang
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ldr pc, _hang
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ldr pc, _hang
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ldr pc, _hang
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ldr pc, _hang
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ldr pc, _hang
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ldr pc, _hang
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_hang:
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.word do_hang
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.word 0x12345678
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.word 0x12345678
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.word 0x12345678
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.word 0x12345678
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.word 0x12345678
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.word 0x12345678
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.word 0x12345678 /* now 16*4=64 */
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#else
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ldr pc, _undefined_instruction
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ldr pc, _software_interrupt
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ldr pc, _prefetch_abort
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ldr pc, _data_abort
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ldr pc, _not_used
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ldr pc, _irq
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ldr pc, _fiq
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_undefined_instruction: .word undefined_instruction
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_software_interrupt: .word software_interrupt
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_prefetch_abort: .word prefetch_abort
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_data_abort: .word data_abort
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_not_used: .word not_used
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_irq: .word irq
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_fiq: .word fiq
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#endif /* CONFIG_PRELOADER */
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.balignl 16,0xdeadbeef
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/*
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* Startup Code (reset vector)
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*
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* do important init only if we don't start from RAM!
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* - relocate armboot to RAM
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* - setup stack
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* - jump to second stage
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*/
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.globl _TEXT_BASE
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_TEXT_BASE:
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.word TEXT_BASE
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#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
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.globl _armboot_start
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_armboot_start:
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.word _start
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#endif
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/*
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* These are defined in the board-specific linker script.
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*/
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.globl _bss_start
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_bss_start:
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.word __bss_start
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.globl _bss_end
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_bss_end:
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.word _end
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#ifdef CONFIG_USE_IRQ
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/* IRQ stack memory (calculated at run-time) */
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.globl IRQ_STACK_START
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IRQ_STACK_START:
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.word 0x0badc0de
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/* IRQ stack memory (calculated at run-time) */
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.globl FIQ_STACK_START
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FIQ_STACK_START:
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.word 0x0badc0de
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#endif /* CONFIG_USE_IRQ */
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#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
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/* IRQ stack memory (calculated at run-time) + 8 bytes */
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.globl IRQ_STACK_START_IN
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IRQ_STACK_START_IN:
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.word 0x0badc0de
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.globl _datarel_start
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_datarel_start:
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.word __datarel_start
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.globl _datarelrolocal_start
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_datarelrolocal_start:
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.word __datarelrolocal_start
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.globl _datarellocal_start
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_datarellocal_start:
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.word __datarellocal_start
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.globl _datarelro_start
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_datarelro_start:
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.word __datarelro_start
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.globl _got_start
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_got_start:
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.word __got_start
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.globl _got_end
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_got_end:
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.word __got_end
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/*
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* the actual reset code
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*/
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reset:
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/*
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* set the cpu to SVC32 mode
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*/
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mrs r0,cpsr
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bic r0,r0,#0x1f
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orr r0,r0,#0xd3
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msr cpsr,r0
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/*
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* we do sys-critical inits only at reboot,
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* not when booting from ram!
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*/
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#ifndef CONFIG_SKIP_LOWLEVEL_INIT
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bl cpu_init_crit
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#endif
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/* Set stackpointer in internal RAM to call board_init_f */
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call_board_init_f:
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ldr sp, =(CONFIG_SYS_INIT_SP_ADDR)
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ldr r0,=0x00000000
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bl board_init_f
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/*------------------------------------------------------------------------------*/
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/*
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* void relocate_code (addr_sp, gd, addr_moni)
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*
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* This "function" does not return, instead it continues in RAM
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* after relocating the monitor code.
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*
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*/
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.globl relocate_code
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relocate_code:
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mov r4, r0 /* save addr_sp */
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mov r5, r1 /* save addr of gd */
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mov r6, r2 /* save addr of destination */
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mov r7, r2 /* save addr of destination */
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/* Set up the stack */
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stack_setup:
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mov sp, r4
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adr r0, _start
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ldr r2, _TEXT_BASE
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ldr r3, _bss_start
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sub r2, r3, r2 /* r2 <- size of armboot */
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add r2, r0, r2 /* r2 <- source end address */
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cmp r0, r6
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beq clear_bss
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#ifndef CONFIG_SKIP_RELOCATE_UBOOT
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copy_loop:
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ldmia r0!, {r9-r10} /* copy from source address [r0] */
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stmia r6!, {r9-r10} /* copy to target address [r1] */
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cmp r0, r2 /* until source end address [r2] */
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blo copy_loop
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#ifndef CONFIG_PRELOADER
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/* fix got entries */
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ldr r1, _TEXT_BASE /* Text base */
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mov r0, r7 /* reloc addr */
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ldr r2, _got_start /* addr in Flash */
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ldr r3, _got_end /* addr in Flash */
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sub r3, r3, r1
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add r3, r3, r0
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sub r2, r2, r1
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add r2, r2, r0
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fixloop:
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ldr r4, [r2]
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sub r4, r4, r1
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add r4, r4, r0
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str r4, [r2]
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add r2, r2, #4
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cmp r2, r3
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bne fixloop
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#endif
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#endif /* #ifndef CONFIG_SKIP_RELOCATE_UBOOT */
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clear_bss:
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#ifndef CONFIG_PRELOADER
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ldr r0, _bss_start
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ldr r1, _bss_end
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ldr r3, _TEXT_BASE /* Text base */
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mov r4, r7 /* reloc addr */
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sub r0, r0, r3
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add r0, r0, r4
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sub r1, r1, r3
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add r1, r1, r4
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mov r2, #0x00000000 /* clear */
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clbss_l:str r2, [r0] /* clear loop... */
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add r0, r0, #4
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cmp r0, r1
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bne clbss_l
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#endif
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/*
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* We are done. Do not return, instead branch to second part of board
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* initialization, now running from RAM.
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*/
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#ifdef CONFIG_ONENAND_IPL
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ldr pc, _start_oneboot
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_start_oneboot: .word start_oneboot
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#else
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ldr r0, _TEXT_BASE
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ldr r2, _board_init_r
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sub r2, r2, r0
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add r2, r2, r7 /* position from board_init_r in RAM */
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/* setup parameters for board_init_r */
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mov r0, r5 /* gd_t */
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mov r1, r7 /* dest_addr */
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/* jump to it ... */
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mov lr, r2
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mov pc, lr
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_board_init_r: .word board_init_r
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#endif
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#else /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
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/****************************************************************************/
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/* */
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/* the actual reset code */
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/* */
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/****************************************************************************/
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reset:
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mrs r0,cpsr /* set the CPU to SVC32 mode */
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bic r0,r0,#0x1f /* (superviser mode, M=10011) */
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orr r0,r0,#0x13
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msr cpsr,r0
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/*
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* we do sys-critical inits only at reboot,
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* not when booting from RAM!
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*/
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#ifndef CONFIG_SKIP_LOWLEVEL_INIT
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bl cpu_init_crit /* we do sys-critical inits */
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#endif /* !CONFIG_SKIP_LOWLEVEL_INIT */
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#ifndef CONFIG_SKIP_RELOCATE_UBOOT
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relocate: /* relocate U-Boot to RAM */
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adr r0, _start /* r0 <- current position of code */
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ldr r1, _TEXT_BASE /* test if we run from flash or RAM */
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#ifndef CONFIG_PRELOADER
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cmp r0, r1 /* don't reloc during debug */
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beq stack_setup
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#endif
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ldr r2, _armboot_start
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ldr r3, _bss_start
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sub r2, r3, r2 /* r2 <- size of armboot */
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add r2, r0, r2 /* r2 <- source end address */
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copy_loop:
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ldmia r0!, {r3-r10} /* copy from source address [r0] */
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stmia r1!, {r3-r10} /* copy to target address [r1] */
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cmp r0, r2 /* until source end address [r2] */
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blo copy_loop
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#endif /* !CONFIG_SKIP_RELOCATE_UBOOT */
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/* Set up the stack */
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stack_setup:
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ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */
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#ifdef CONFIG_PRELOADER
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sub sp, r0, #128 /* leave 32 words for abort-stack */
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#else
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sub r0, r0, #CONFIG_SYS_MALLOC_LEN /* malloc area */
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sub r0, r0, #CONFIG_SYS_GBL_DATA_SIZE /* bdinfo */
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#ifdef CONFIG_USE_IRQ
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sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
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#endif /* CONFIG_USE_IRQ */
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sub sp, r0, #12 /* leave 3 words for abort-stack */
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bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
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#endif
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clear_bss:
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ldr r0, _bss_start /* find start of bss segment */
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ldr r1, _bss_end /* stop here */
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mov r2, #0x00000000 /* clear */
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#ifndef CONFIG_PRELOADER
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clbss_l:str r2, [r0] /* clear loop... */
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add r0, r0, #4
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cmp r0, r1
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blo clbss_l
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#endif
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ldr pc, _start_armboot
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#ifdef CONFIG_ONENAND_IPL
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_start_armboot: .word start_oneboot
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#else
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_start_armboot: .word start_armboot
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#endif
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#endif /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
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/****************************************************************************/
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/* */
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/* CPU_init_critical registers */
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/* */
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/* - setup important registers */
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/* - setup memory timing */
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/* */
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/****************************************************************************/
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/* mk@tbd: Fix this! */
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#undef RCSR
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#undef ICMR
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#undef OSMR3
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#undef OSCR
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#undef OWER
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#undef OIER
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#undef CCCR
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/* Interrupt-Controller base address */
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IC_BASE: .word 0x40d00000
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#define ICMR 0x04
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/* Reset-Controller */
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RST_BASE: .word 0x40f00030
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#define RCSR 0x00
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/* Operating System Timer */
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OSTIMER_BASE: .word 0x40a00000
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#define OSMR3 0x0C
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#define OSCR 0x10
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#define OWER 0x18
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#define OIER 0x1C
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/* Clock Manager Registers */
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#ifdef CONFIG_CPU_MONAHANS
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# ifndef CONFIG_SYS_MONAHANS_RUN_MODE_OSC_RATIO
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# error "You have to define CONFIG_SYS_MONAHANS_RUN_MODE_OSC_RATIO!!"
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# endif /* !CONFIG_SYS_MONAHANS_RUN_MODE_OSC_RATIO */
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# ifndef CONFIG_SYS_MONAHANS_TURBO_RUN_MODE_RATIO
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# define CONFIG_SYS_MONAHANS_TURBO_RUN_MODE_RATIO 0x1
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# endif /* !CONFIG_SYS_MONAHANS_TURBO_RUN_MODE_RATIO */
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#else /* !CONFIG_CPU_MONAHANS */
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#ifdef CONFIG_SYS_CPUSPEED
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CC_BASE: .word 0x41300000
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#define CCCR 0x00
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cpuspeed: .word CONFIG_SYS_CPUSPEED
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#else /* !CONFIG_SYS_CPUSPEED */
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#error "You have to define CONFIG_SYS_CPUSPEED!!"
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#endif /* CONFIG_SYS_CPUSPEED */
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#endif /* CONFIG_CPU_MONAHANS */
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/* takes care the CP15 update has taken place */
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.macro CPWAIT reg
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mrc p15,0,\reg,c2,c0,0
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mov \reg,\reg
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sub pc,pc,#4
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.endm
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cpu_init_crit:
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/* mask all IRQs */
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#ifndef CONFIG_CPU_MONAHANS
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ldr r0, IC_BASE
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mov r1, #0x00
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str r1, [r0, #ICMR]
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#else /* CONFIG_CPU_MONAHANS */
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/* Step 1 - Enable CP6 permission */
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mrc p15, 0, r1, c15, c1, 0 @ read CPAR
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orr r1, r1, #0x40
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mcr p15, 0, r1, c15, c1, 0
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CPWAIT r1
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/* Step 2 - Mask ICMR & ICMR2 */
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mov r1, #0
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mcr p6, 0, r1, c1, c0, 0 @ ICMR
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mcr p6, 0, r1, c7, c0, 0 @ ICMR2
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/* turn off all clocks but the ones we will definitly require */
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ldr r1, =CKENA
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ldr r2, =(CKENA_22_FFUART | CKENA_10_SRAM | CKENA_9_SMC | CKENA_8_DMC)
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str r2, [r1]
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ldr r1, =CKENB
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ldr r2, =(CKENB_6_IRQ)
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str r2, [r1]
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#endif /* !CONFIG_CPU_MONAHANS */
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/* set clock speed */
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#ifdef CONFIG_CPU_MONAHANS
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ldr r0, =ACCR
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ldr r1, =(((CONFIG_SYS_MONAHANS_TURBO_RUN_MODE_RATIO<<8) & ACCR_XN_MASK) | (CONFIG_SYS_MONAHANS_RUN_MODE_OSC_RATIO & ACCR_XL_MASK))
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str r1, [r0]
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#else /* !CONFIG_CPU_MONAHANS */
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#ifdef CONFIG_SYS_CPUSPEED
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ldr r0, CC_BASE
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ldr r1, cpuspeed
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str r1, [r0, #CCCR]
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mov r0, #2
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mcr p14, 0, r0, c6, c0, 0
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setspeed_done:
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#endif /* CONFIG_SYS_CPUSPEED */
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#endif /* CONFIG_CPU_MONAHANS */
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/*
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* before relocating, we have to setup RAM timing
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* because memory timing is board-dependend, you will
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* find a lowlevel_init.S in your board directory.
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*/
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mov ip, lr
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bl lowlevel_init
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mov lr, ip
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/* Memory interfaces are working. Disable MMU and enable I-cache. */
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/* mk: hmm, this is not in the monahans docs, leave it now but
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* check here if it doesn't work :-) */
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ldr r0, =0x2001 /* enable access to all coproc. */
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mcr p15, 0, r0, c15, c1, 0
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CPWAIT r0
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mcr p15, 0, r0, c7, c10, 4 /* drain the write & fill buffers */
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CPWAIT r0
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mcr p15, 0, r0, c7, c7, 0 /* flush Icache, Dcache and BTB */
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CPWAIT r0
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mcr p15, 0, r0, c8, c7, 0 /* flush instuction and data TLBs */
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CPWAIT r0
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/* Enable the Icache */
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/*
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mrc p15, 0, r0, c1, c0, 0
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orr r0, r0, #0x1800
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mcr p15, 0, r0, c1, c0, 0
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CPWAIT
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*/
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mov pc, lr
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#ifndef CONFIG_PRELOADER
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/****************************************************************************/
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/* */
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/* Interrupt handling */
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/* */
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/****************************************************************************/
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/* IRQ stack frame */
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#define S_FRAME_SIZE 72
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#define S_OLD_R0 68
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#define S_PSR 64
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#define S_PC 60
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#define S_LR 56
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#define S_SP 52
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#define S_IP 48
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#define S_FP 44
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#define S_R10 40
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#define S_R9 36
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#define S_R8 32
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#define S_R7 28
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#define S_R6 24
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#define S_R5 20
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#define S_R4 16
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#define S_R3 12
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#define S_R2 8
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#define S_R1 4
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#define S_R0 0
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#define MODE_SVC 0x13
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/* use bad_save_user_regs for abort/prefetch/undef/swi ... */
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.macro bad_save_user_regs
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sub sp, sp, #S_FRAME_SIZE
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stmia sp, {r0 - r12} /* Calling r0-r12 */
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add r8, sp, #S_PC
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#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
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ldr r2, _armboot_start
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sub r2, r2, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
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sub r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ set base 2 words into abort stack
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#else
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ldr r2, IRQ_STACK_START_IN
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#endif
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ldmia r2, {r2 - r4} /* get pc, cpsr, old_r0 */
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add r0, sp, #S_FRAME_SIZE /* restore sp_SVC */
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add r5, sp, #S_SP
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mov r1, lr
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stmia r5, {r0 - r4} /* save sp_SVC, lr_SVC, pc, cpsr, old_r */
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mov r0, sp
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.endm
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/* use irq_save_user_regs / irq_restore_user_regs for */
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/* IRQ/FIQ handling */
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.macro irq_save_user_regs
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sub sp, sp, #S_FRAME_SIZE
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stmia sp, {r0 - r12} /* Calling r0-r12 */
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add r8, sp, #S_PC
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stmdb r8, {sp, lr}^ /* Calling SP, LR */
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str lr, [r8, #0] /* Save calling PC */
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mrs r6, spsr
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str r6, [r8, #4] /* Save CPSR */
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str r0, [r8, #8] /* Save OLD_R0 */
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mov r0, sp
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.endm
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|
|
|
.macro irq_restore_user_regs
|
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ldmia sp, {r0 - lr}^ @ Calling r0 - lr
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|
mov r0, r0
|
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ldr lr, [sp, #S_PC] @ Get PC
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add sp, sp, #S_FRAME_SIZE
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subs pc, lr, #4 @ return & move spsr_svc into cpsr
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.endm
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|
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.macro get_bad_stack
|
|
#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
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|
ldr r13, _armboot_start @ setup our mode stack
|
|
sub r13, r13, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
|
|
sub r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack
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#else
|
|
ldr r13, IRQ_STACK_START_IN @ setup our mode stack
|
|
#endif
|
|
|
|
str lr, [r13] @ save caller lr / spsr
|
|
mrs lr, spsr
|
|
str lr, [r13, #4]
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|
|
|
mov r13, #MODE_SVC @ prepare SVC-Mode
|
|
msr spsr_c, r13
|
|
mov lr, pc
|
|
movs pc, lr
|
|
.endm
|
|
|
|
.macro get_irq_stack @ setup IRQ stack
|
|
ldr sp, IRQ_STACK_START
|
|
.endm
|
|
|
|
.macro get_fiq_stack @ setup FIQ stack
|
|
ldr sp, FIQ_STACK_START
|
|
.endm
|
|
#endif /* CONFIG_PRELOADER */
|
|
|
|
|
|
/****************************************************************************/
|
|
/* */
|
|
/* exception handlers */
|
|
/* */
|
|
/****************************************************************************/
|
|
|
|
#ifdef CONFIG_PRELOADER
|
|
.align 5
|
|
do_hang:
|
|
ldr sp, _TEXT_BASE /* use 32 words abort stack */
|
|
bl hang /* hang and never return */
|
|
#else /* !CONFIG_PRELOADER */
|
|
.align 5
|
|
undefined_instruction:
|
|
get_bad_stack
|
|
bad_save_user_regs
|
|
bl do_undefined_instruction
|
|
|
|
.align 5
|
|
software_interrupt:
|
|
get_bad_stack
|
|
bad_save_user_regs
|
|
bl do_software_interrupt
|
|
|
|
.align 5
|
|
prefetch_abort:
|
|
get_bad_stack
|
|
bad_save_user_regs
|
|
bl do_prefetch_abort
|
|
|
|
.align 5
|
|
data_abort:
|
|
get_bad_stack
|
|
bad_save_user_regs
|
|
bl do_data_abort
|
|
|
|
.align 5
|
|
not_used:
|
|
get_bad_stack
|
|
bad_save_user_regs
|
|
bl do_not_used
|
|
|
|
#ifdef CONFIG_USE_IRQ
|
|
|
|
.align 5
|
|
irq:
|
|
get_irq_stack
|
|
irq_save_user_regs
|
|
bl do_irq
|
|
irq_restore_user_regs
|
|
|
|
.align 5
|
|
fiq:
|
|
get_fiq_stack
|
|
irq_save_user_regs /* someone ought to write a more */
|
|
bl do_fiq /* effiction fiq_save_user_regs */
|
|
irq_restore_user_regs
|
|
|
|
#else /* !CONFIG_USE_IRQ */
|
|
|
|
.align 5
|
|
irq:
|
|
get_bad_stack
|
|
bad_save_user_regs
|
|
bl do_irq
|
|
|
|
.align 5
|
|
fiq:
|
|
get_bad_stack
|
|
bad_save_user_regs
|
|
bl do_fiq
|
|
#endif /* CONFIG_PRELOADER */
|
|
#endif /* CONFIG_USE_IRQ */
|
|
|
|
/****************************************************************************/
|
|
/* */
|
|
/* Reset function: the PXA250 doesn't have a reset function, so we have to */
|
|
/* perform a watchdog timeout for a soft reset. */
|
|
/* */
|
|
/****************************************************************************/
|
|
|
|
.align 5
|
|
.globl reset_cpu
|
|
|
|
/* FIXME: this code is PXA250 specific. How is this handled on */
|
|
/* other XScale processors? */
|
|
|
|
reset_cpu:
|
|
|
|
/* We set OWE:WME (watchdog enable) and wait until timeout happens */
|
|
|
|
ldr r0, OSTIMER_BASE
|
|
ldr r1, [r0, #OWER]
|
|
orr r1, r1, #0x0001 /* bit0: WME */
|
|
str r1, [r0, #OWER]
|
|
|
|
/* OS timer does only wrap every 1165 seconds, so we have to set */
|
|
/* the match register as well. */
|
|
|
|
ldr r1, [r0, #OSCR] /* read OS timer */
|
|
add r1, r1, #0x800 /* let OSMR3 match after */
|
|
add r1, r1, #0x800 /* 4096*(1/3.6864MHz)=1ms */
|
|
str r1, [r0, #OSMR3]
|
|
|
|
reset_endless:
|
|
|
|
b reset_endless
|