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https://github.com/AsahiLinux/u-boot
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8aeba629cc
- add the 2 new compatible used by STM32MP157 "st,stm32mp157-pinctrl" "st,stm32mp157-z-pinctrl" - update the mask for the port Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
203 lines
5.1 KiB
C
203 lines
5.1 KiB
C
#include <common.h>
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#include <dm.h>
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#include <dm/pinctrl.h>
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#include <asm/arch/gpio.h>
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#include <asm/gpio.h>
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#include <asm/io.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define MAX_PINS_ONE_IP 70
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#define MODE_BITS_MASK 3
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#define OSPEED_MASK 3
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#define PUPD_MASK 3
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#define OTYPE_MSK 1
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#define AFR_MASK 0xF
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static int stm32_gpio_config(struct gpio_desc *desc,
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const struct stm32_gpio_ctl *ctl)
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{
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struct stm32_gpio_priv *priv = dev_get_priv(desc->dev);
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struct stm32_gpio_regs *regs = priv->regs;
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u32 index;
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if (!ctl || ctl->af > 15 || ctl->mode > 3 || ctl->otype > 1 ||
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ctl->pupd > 2 || ctl->speed > 3)
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return -EINVAL;
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index = (desc->offset & 0x07) * 4;
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clrsetbits_le32(®s->afr[desc->offset >> 3], AFR_MASK << index,
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ctl->af << index);
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index = desc->offset * 2;
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clrsetbits_le32(®s->moder, MODE_BITS_MASK << index,
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ctl->mode << index);
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clrsetbits_le32(®s->ospeedr, OSPEED_MASK << index,
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ctl->speed << index);
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clrsetbits_le32(®s->pupdr, PUPD_MASK << index, ctl->pupd << index);
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index = desc->offset;
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clrsetbits_le32(®s->otyper, OTYPE_MSK << index, ctl->otype << index);
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return 0;
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}
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static int prep_gpio_dsc(struct stm32_gpio_dsc *gpio_dsc, u32 port_pin)
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{
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gpio_dsc->port = (port_pin & 0x1F000) >> 12;
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gpio_dsc->pin = (port_pin & 0x0F00) >> 8;
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debug("%s: GPIO:port= %d, pin= %d\n", __func__, gpio_dsc->port,
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gpio_dsc->pin);
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return 0;
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}
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static int prep_gpio_ctl(struct stm32_gpio_ctl *gpio_ctl, u32 gpio_fn, int node)
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{
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gpio_fn &= 0x00FF;
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gpio_ctl->af = 0;
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switch (gpio_fn) {
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case 0:
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gpio_ctl->mode = STM32_GPIO_MODE_IN;
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break;
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case 1 ... 16:
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gpio_ctl->mode = STM32_GPIO_MODE_AF;
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gpio_ctl->af = gpio_fn - 1;
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break;
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case 17:
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gpio_ctl->mode = STM32_GPIO_MODE_AN;
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break;
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default:
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gpio_ctl->mode = STM32_GPIO_MODE_OUT;
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break;
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}
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gpio_ctl->speed = fdtdec_get_int(gd->fdt_blob, node, "slew-rate", 0);
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if (fdtdec_get_bool(gd->fdt_blob, node, "drive-open-drain"))
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gpio_ctl->otype = STM32_GPIO_OTYPE_OD;
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else
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gpio_ctl->otype = STM32_GPIO_OTYPE_PP;
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if (fdtdec_get_bool(gd->fdt_blob, node, "bias-pull-up"))
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gpio_ctl->pupd = STM32_GPIO_PUPD_UP;
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else if (fdtdec_get_bool(gd->fdt_blob, node, "bias-pull-down"))
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gpio_ctl->pupd = STM32_GPIO_PUPD_DOWN;
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else
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gpio_ctl->pupd = STM32_GPIO_PUPD_NO;
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debug("%s: gpio fn= %d, slew-rate= %x, op type= %x, pull-upd is = %x\n",
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__func__, gpio_fn, gpio_ctl->speed, gpio_ctl->otype,
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gpio_ctl->pupd);
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return 0;
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}
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static int stm32_pinctrl_config(int offset)
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{
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u32 pin_mux[MAX_PINS_ONE_IP];
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int rv, len;
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/*
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* check for "pinmux" property in each subnode (e.g. pins1 and pins2 for
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* usart1) of pin controller phandle "pinctrl-0"
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* */
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fdt_for_each_subnode(offset, gd->fdt_blob, offset) {
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struct stm32_gpio_dsc gpio_dsc;
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struct stm32_gpio_ctl gpio_ctl;
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int i;
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len = fdtdec_get_int_array_count(gd->fdt_blob, offset,
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"pinmux", pin_mux,
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ARRAY_SIZE(pin_mux));
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debug("%s: no of pinmux entries= %d\n", __func__, len);
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if (len < 0)
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return -EINVAL;
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for (i = 0; i < len; i++) {
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struct gpio_desc desc;
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debug("%s: pinmux = %x\n", __func__, *(pin_mux + i));
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prep_gpio_dsc(&gpio_dsc, *(pin_mux + i));
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prep_gpio_ctl(&gpio_ctl, *(pin_mux + i), offset);
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rv = uclass_get_device_by_seq(UCLASS_GPIO,
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gpio_dsc.port,
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&desc.dev);
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if (rv)
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return rv;
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desc.offset = gpio_dsc.pin;
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rv = stm32_gpio_config(&desc, &gpio_ctl);
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debug("%s: rv = %d\n\n", __func__, rv);
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if (rv)
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return rv;
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}
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}
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return 0;
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}
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#if CONFIG_IS_ENABLED(PINCTRL_FULL)
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static int stm32_pinctrl_set_state(struct udevice *dev, struct udevice *config)
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{
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return stm32_pinctrl_config(dev_of_offset(config));
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}
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#else /* PINCTRL_FULL */
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static int stm32_pinctrl_set_state_simple(struct udevice *dev,
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struct udevice *periph)
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{
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const void *fdt = gd->fdt_blob;
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const fdt32_t *list;
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uint32_t phandle;
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int config_node;
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int size, i, ret;
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list = fdt_getprop(fdt, dev_of_offset(periph), "pinctrl-0", &size);
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if (!list)
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return -EINVAL;
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debug("%s: periph->name = %s\n", __func__, periph->name);
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size /= sizeof(*list);
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for (i = 0; i < size; i++) {
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phandle = fdt32_to_cpu(*list++);
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config_node = fdt_node_offset_by_phandle(fdt, phandle);
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if (config_node < 0) {
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pr_err("prop pinctrl-0 index %d invalid phandle\n", i);
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return -EINVAL;
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}
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ret = stm32_pinctrl_config(config_node);
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if (ret)
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return ret;
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}
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return 0;
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}
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#endif /* PINCTRL_FULL */
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static struct pinctrl_ops stm32_pinctrl_ops = {
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#if CONFIG_IS_ENABLED(PINCTRL_FULL)
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.set_state = stm32_pinctrl_set_state,
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#else /* PINCTRL_FULL */
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.set_state_simple = stm32_pinctrl_set_state_simple,
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#endif /* PINCTRL_FULL */
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};
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static const struct udevice_id stm32_pinctrl_ids[] = {
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{ .compatible = "st,stm32f429-pinctrl" },
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{ .compatible = "st,stm32f469-pinctrl" },
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{ .compatible = "st,stm32f746-pinctrl" },
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{ .compatible = "st,stm32h743-pinctrl" },
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{ .compatible = "st,stm32mp157-pinctrl" },
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{ .compatible = "st,stm32mp157-z-pinctrl" },
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{ }
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};
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U_BOOT_DRIVER(pinctrl_stm32) = {
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.name = "pinctrl_stm32",
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.id = UCLASS_PINCTRL,
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.of_match = stm32_pinctrl_ids,
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.ops = &stm32_pinctrl_ops,
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.bind = dm_scan_fdt_dev,
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};
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