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CS Systemes d'Information (CSSI) manufactures two boards, named MCR3000 and CMPC885 which are respectively based on MPC866 and MPC885 processors. This patch adds support for the first board. Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
144 lines
3.9 KiB
C
144 lines
3.9 KiB
C
/*
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* Copyright (C) 2010-2017 CS Systemes d'Information
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* Florent Trinh Thai <florent.trinh-thai@c-s.fr>
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* Christophe Leroy <christophe.leroy@c-s.fr>
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*
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* Board specific routines for the MCR3000 board
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <hwconfig.h>
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#include <mpc8xx.h>
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#include <fdt_support.h>
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#include <asm/io.h>
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DECLARE_GLOBAL_DATA_PTR;
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static const uint cs1_dram_table_66[] = {
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/* DRAM - single read. (offset 0 in upm RAM) */
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0x0F3DFC04, 0x0FEFBC04, 0x00BE7804, 0x0FFDF400,
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0x1FFFFC05, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
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/* DRAM - burst read. (offset 8 in upm RAM) */
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0x0F3DFC04, 0x0FEFBC04, 0x00BF7C04, 0x00FFFC00,
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0x00FFFC00, 0x00FEF800, 0x0FFDF400, 0x1FFFFC05,
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0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
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0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
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/* DRAM - single write. (offset 18 in upm RAM) */
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0x0F3DFC04, 0x0FEFB800, 0x00BF7404, 0x0FFEF804,
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0x0FFDF404, 0x1FFFFC05, 0xFFFFFFFF, 0xFFFFFFFF,
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/* DRAM - burst write. (offset 20 in upm RAM) */
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0x0F3DFC04, 0x0FEFB800, 0x00BF7400, 0x00FFFC00,
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0x00FFFC00, 0x00FFFC04, 0x0FFEF804, 0x0FFDF404,
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0x1FFFFC05, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
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0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
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/* refresh (offset 30 in upm RAM) */
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0x0FFDF404, 0x0FFEBC04, 0x0FFD7C84, 0x0FFFFC04,
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0x0FFFFC04, 0x0FFFFC04, 0x1FFFFC85, 0xFFFFFFFF,
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/* init */
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0x0FEEB874, 0x0FBD7474, 0x1FFFFC45, 0xFFFFFFFF,
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/* exception. (offset 3c in upm RAM) */
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0xFFFFFC05, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
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};
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int ft_board_setup(void *blob, bd_t *bd)
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{
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const char *sync = "receive";
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ft_cpu_setup(blob, bd);
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/* BRG */
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do_fixup_by_path_u32(blob, "/soc/cpm", "brg-frequency",
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bd->bi_busfreq, 1);
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/* MAC addr */
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fdt_fixup_ethernet(blob);
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/* Bus Frequency for CPM */
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do_fixup_by_path_u32(blob, "/soc", "bus-frequency", bd->bi_busfreq, 1);
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/* E1 interface - Set data rate */
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do_fixup_by_path_u32(blob, "/localbus/e1-wan", "data-rate", 2, 1);
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/* E1 interface - Set channel phase to 0 */
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do_fixup_by_path_u32(blob, "/localbus/e1-wan", "channel-phase", 0, 1);
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/* E1 interface - rising edge sync pulse transmit */
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do_fixup_by_path(blob, "/localbus/e1-wan", "rising-edge-sync-pulse",
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sync, strlen(sync), 1);
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return 0;
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}
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int checkboard(void)
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{
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serial_puts("BOARD: MCR3000 CSSI\n");
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return 0;
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}
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int dram_init(void)
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{
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immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
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memctl8xx_t __iomem *memctl = &immap->im_memctl;
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printf("UPMA init for SDRAM (CAS latency 2), ");
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printf("init address 0x%08x, size ", (int)dram_init);
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/* Configure UPMA for cs1 */
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upmconfig(UPMA, (uint *)cs1_dram_table_66,
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sizeof(cs1_dram_table_66) / sizeof(uint));
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udelay(10);
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out_be16(&memctl->memc_mptpr, 0x0200);
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out_be32(&memctl->memc_mamr, 0x14904000);
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udelay(10);
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out_be32(&memctl->memc_or1, CONFIG_SYS_OR1_PRELIM);
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out_be32(&memctl->memc_br1, CONFIG_SYS_BR1_PRELIM);
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udelay(10);
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out_be32(&memctl->memc_mcr, 0x80002830);
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out_be32(&memctl->memc_mar, 0x00000088);
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out_be32(&memctl->memc_mcr, 0x80002038);
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udelay(200);
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gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
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SDRAM_MAX_SIZE);
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return 0;
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}
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int misc_init_r(void)
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{
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immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
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iop8xx_t __iomem *iop = &immr->im_ioport;
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/* Set port C13 as GPIO (BTN_ACQ_AL) */
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clrbits_be16(&iop->iop_pcpar, 0x4);
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clrbits_be16(&iop->iop_pcdir, 0x4);
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/* if BTN_ACQ_AL is pressed then bootdelay is changed to 60 second */
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if ((in_be16(&iop->iop_pcdat) & 0x0004) == 0)
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setenv("bootdelay", "60");
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return 0;
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}
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int board_early_init_f(void)
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{
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immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
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/*
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* Erase FPGA(s) for reboot
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*/
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clrbits_be32(&immr->im_cpm.cp_pbdat, 0x00020000); /* PROGFPGA down */
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setbits_be32(&immr->im_cpm.cp_pbdir, 0x00020000); /* PROGFPGA output */
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udelay(1); /* Wait more than 300ns */
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setbits_be32(&immr->im_cpm.cp_pbdat, 0x00020000); /* PROGFPGA up */
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return 0;
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}
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