mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-13 06:42:56 +00:00
e00f76cee9
Move this option to Kconfig and tidy up existing uses. Signed-off-by: Simon Glass <sjg@chromium.org>
384 lines
12 KiB
C
384 lines
12 KiB
C
/*
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* Copyright (C) 2011 Ilya Yanok, Emcraft Systems
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*
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* Based on omap3_evm_config.h
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* High Level Configuration Options
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*/
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#define CONFIG_OMAP /* in a TI OMAP core */
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#define CONFIG_OMAP3_MCX /* working with mcx */
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#define CONFIG_OMAP_GPIO
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#define CONFIG_OMAP_COMMON
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/* Common ARM Erratas */
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#define CONFIG_ARM_ERRATA_454179
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#define CONFIG_ARM_ERRATA_430973
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#define CONFIG_ARM_ERRATA_621766
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#define MACH_TYPE_MCX 3656
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#define CONFIG_MACH_TYPE MACH_TYPE_MCX
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#define CONFIG_BOARD_LATE_INIT
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#define CONFIG_EMIF4 /* The chip has EMIF4 controller */
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#include <asm/arch/cpu.h> /* get chip and board defs */
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#include <asm/arch/omap.h>
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/*
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* Leave it at 0x80008000 to allow booting new u-boot.bin with X-loader
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* and older u-boot.bin with the new U-Boot SPL.
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*/
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#define CONFIG_SYS_TEXT_BASE 0x80008000
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/*
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* Display CPU and Board information
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*/
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#define CONFIG_DISPLAY_CPUINFO
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#define CONFIG_DISPLAY_BOARDINFO
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/* Clock Defines */
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#define V_OSCK 26000000 /* Clock output from T2 */
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#define V_SCLK (V_OSCK >> 1)
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#define CONFIG_MISC_INIT_R
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#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
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#define CONFIG_SETUP_MEMORY_TAGS
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#define CONFIG_INITRD_TAG
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#define CONFIG_REVISION_TAG
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/*
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* Size of malloc() pool
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*/
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#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */
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#define CONFIG_SYS_MALLOC_LEN (1024 << 10)
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/*
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* DDR related
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*/
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#define CONFIG_SYS_CS0_SIZE (256 * 1024 * 1024)
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/*
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* Hardware drivers
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*/
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/*
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* NS16550 Configuration
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*/
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#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
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#define CONFIG_SYS_NS16550_SERIAL
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#define CONFIG_SYS_NS16550_REG_SIZE (-4)
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#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
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/*
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* select serial console configuration
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*/
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#define CONFIG_CONS_INDEX 3
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#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
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#define CONFIG_SERIAL3 3 /* UART3 */
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/* allow to overwrite serial and ethaddr */
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#define CONFIG_ENV_OVERWRITE
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#define CONFIG_BAUDRATE 115200
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#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
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115200}
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#define CONFIG_MMC
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#define CONFIG_OMAP_HSMMC
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#define CONFIG_GENERIC_MMC
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#define CONFIG_DOS_PARTITION
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/* EHCI */
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#define CONFIG_OMAP3_GPIO_2
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#define CONFIG_OMAP3_GPIO_5
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#define CONFIG_USB_EHCI
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#define CONFIG_USB_EHCI_OMAP
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#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 57
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#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
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#define CONFIG_USB_HOST_ETHER
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#define CONFIG_USB_ETHER_ASIX
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#define CONFIG_USB_ETHER_MCS7830
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/* commands to include */
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#define CONFIG_CMD_JFFS2 /* JFFS2 Support */
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#define CONFIG_CMD_DATE
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#define CONFIG_CMD_NAND /* NAND support */
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#define CONFIG_CMD_UBI
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#define CONFIG_CMD_UBIFS
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#define CONFIG_RBTREE
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#define CONFIG_LZO
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#define CONFIG_MTD_PARTITIONS
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#define CONFIG_MTD_DEVICE
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#define CONFIG_CMD_MTDPARTS
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#define CONFIG_SYS_NO_FLASH
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#define CONFIG_SYS_I2C
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#define CONFIG_SYS_OMAP24_I2C_SPEED 100000
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#define CONFIG_SYS_OMAP24_I2C_SLAVE 1
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#define CONFIG_SYS_I2C_OMAP34XX
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/* RTC */
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#define CONFIG_RTC_DS1337
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#define CONFIG_SYS_I2C_RTC_ADDR 0x68
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/*
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* Board NAND Info.
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*/
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#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
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/* to access nand */
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#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
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/* to access */
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/* nand at CS0 */
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#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */
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/* NAND devices */
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#define CONFIG_JFFS2_NAND
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/* nand device jffs2 lives on */
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#define CONFIG_JFFS2_DEV "nand0"
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/* start of jffs2 partition */
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#define CONFIG_JFFS2_PART_OFFSET 0x680000
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#define CONFIG_JFFS2_PART_SIZE 0xf980000 /* sz of jffs2 part */
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/* Environment information */
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#define CONFIG_BOOTFILE "uImage"
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/* Setup MTD for NAND on the SOM */
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#define MTDIDS_DEFAULT "nand0=omap2-nand.0"
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#define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:512k(MLO)," \
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"1m(u-boot),256k(env1)," \
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"256k(env2),6m(kernel),6m(k_recovery)," \
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"8m(fs_recovery),-(common_data)"
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#define CONFIG_HOSTNAME mcx
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"adddbg=setenv bootargs ${bootargs} trace_buf_size=64M\0" \
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"adddebug=setenv bootargs ${bootargs} earlyprintk=serial\0" \
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"addeth=setenv bootargs ${bootargs} ethaddr=${ethaddr}\0" \
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"addfb=setenv bootargs ${bootargs} vram=6M " \
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"omapfb.vram=1:2M,2:2M,3:2M omapdss.def_disp=lcd\0" \
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"addip_sta=setenv bootargs ${bootargs} " \
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"ip=${ipaddr}:${serverip}:${gatewayip}:" \
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"${netmask}:${hostname}:eth0:off\0" \
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"addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0" \
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"addip=if test -n ${ipdyn};then run addip_dyn;" \
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"else run addip_sta;fi\0" \
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"addmisc=setenv bootargs ${bootargs} ${misc}\0" \
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"addtty=setenv bootargs ${bootargs} " \
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"console=${consoledev},${baudrate}\0" \
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"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
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"baudrate=115200\0" \
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"consoledev=ttyO2\0" \
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"hostname=" __stringify(CONFIG_HOSTNAME) "\0" \
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"loadaddr=0x82000000\0" \
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"load=tftp ${loadaddr} ${u-boot}\0" \
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"load_k=tftp ${loadaddr} ${bootfile}\0" \
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"loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \
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"loadmlo=tftp ${loadaddr} ${mlo}\0" \
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"mlo=" __stringify(CONFIG_HOSTNAME) "/MLO\0" \
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"mmcargs=root=/dev/mmcblk0p2 rw " \
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"rootfstype=ext3 rootwait\0" \
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"mmcboot=echo Booting from mmc ...; " \
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"run mmcargs; " \
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"run addip addtty addmtd addfb addeth addmisc;" \
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"run loaduimage; " \
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"bootm ${loadaddr}\0" \
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"net_nfs=run load_k; " \
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"run nfsargs; " \
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"run addip addtty addmtd addfb addeth addmisc;" \
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"bootm ${loadaddr}\0" \
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"nfsargs=setenv bootargs root=/dev/nfs rw " \
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"nfsroot=${serverip}:${rootpath}\0" \
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"u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.img\0" \
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"uboot_addr=0x80000\0" \
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"update=nandecc sw;nand erase ${uboot_addr} 100000;" \
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"nand write ${loadaddr} ${uboot_addr} 80000\0" \
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"updatemlo=nandecc hw;nand erase 0 20000;" \
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"nand write ${loadaddr} 0 20000\0" \
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"upd=if run load;then echo Updating u-boot;if run update;" \
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"then echo U-Boot updated;" \
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"else echo Error updating u-boot !;" \
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"echo Board without bootloader !!;" \
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"fi;" \
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"else echo U-Boot not downloaded..exiting;fi\0" \
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"loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \
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"bootscript=echo Running bootscript from mmc ...; " \
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"source ${loadaddr}\0" \
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"nandargs=setenv bootargs ubi.mtd=7 " \
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"root=ubi0:rootfs rootfstype=ubifs\0" \
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"nandboot=echo Booting from nand ...; " \
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"run nandargs; " \
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"ubi part nand0,4;" \
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"ubi readvol ${loadaddr} kernel;" \
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"run addtty addmtd addfb addeth addmisc;" \
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"bootm ${loadaddr}\0" \
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"preboot=ubi part nand0,7;" \
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"ubi readvol ${loadaddr} splash;" \
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"bmp display ${loadaddr};" \
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"gpio set 55\0" \
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"swupdate_args=setenv bootargs root=/dev/ram " \
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"quiet loglevel=1 " \
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"consoleblank=0 ${swupdate_misc}\0" \
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"swupdate=echo Running Sw-Update...;" \
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"if printenv mtdparts;then echo Starting SwUpdate...; " \
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"else mtdparts default;fi; " \
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"ubi part nand0,5;" \
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"ubi readvol 0x82000000 kernel_recovery;" \
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"ubi part nand0,6;" \
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"ubi readvol 0x84000000 fs_recovery;" \
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"run swupdate_args; " \
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"setenv bootargs ${bootargs} " \
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"${mtdparts} " \
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"vram=6M omapfb.vram=1:2M,2:2M,3:2M " \
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"omapdss.def_disp=lcd;" \
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"bootm 0x82000000 0x84000000\0" \
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"bootcmd=mmc rescan;if fatload mmc 0 82000000 loadbootscr.scr;" \
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"then source 82000000;else run nandboot;fi\0"
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#define CONFIG_AUTO_COMPLETE
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#define CONFIG_CMDLINE_EDITING
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/*
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* Miscellaneous configurable options
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*/
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#define CONFIG_SYS_LONGHELP /* undef to save memory */
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#define CONFIG_SYS_CBSIZE 1024/* Console I/O Buffer Size */
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/* Print Buffer Size */
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
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sizeof(CONFIG_SYS_PROMPT) + 16)
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#define CONFIG_SYS_MAXARGS 16 /* max number of command */
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/* args */
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/* Boot Argument Buffer Size */
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#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
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/* memtest works on */
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#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0)
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#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
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0x01F00000) /* 31MB */
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#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */
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/* address */
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#define CONFIG_PREBOOT
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/*
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* AM3517 has 12 GP timers, they can be driven by the system clock
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* (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
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* This rate is divided by a local divisor.
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*/
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#define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2
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#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
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/*
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* Physical Memory Map
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*/
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#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
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#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
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#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
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/*
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* FLASH and environment organization
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*/
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/* **** PISMO SUPPORT *** */
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#define CONFIG_NAND
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#define CONFIG_SYS_NAND_BUSWIDTH_16BIT
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#define CONFIG_NAND_OMAP_GPMC
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#define CONFIG_NAND_OMAP_GPMC_PREFETCH
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#define CONFIG_ENV_IS_IN_NAND
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#define SMNAND_ENV_OFFSET 0x180000 /* environment starts here */
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/* Redundant Environment */
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#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
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#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
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#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
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#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \
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2 * CONFIG_SYS_ENV_SECT_SIZE)
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#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
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/* Flash banks JFFS2 should use */
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#define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \
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CONFIG_SYS_MAX_NAND_DEVICE)
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#define CONFIG_SYS_JFFS2_MEM_NAND
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/* use flash_info[2] */
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#define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS
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#define CONFIG_SYS_JFFS2_NUM_BANKS 1
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#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
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#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
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#define CONFIG_SYS_INIT_RAM_SIZE 0x800
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#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
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CONFIG_SYS_INIT_RAM_SIZE - \
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GENERATED_GBL_DATA_SIZE)
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/* Defines for SPL */
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#define CONFIG_SPL_FRAMEWORK
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#define CONFIG_SPL_BOARD_INIT
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#define CONFIG_SPL_NAND_SIMPLE
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#define CONFIG_SPL_NAND_BASE
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#define CONFIG_SPL_NAND_DRIVERS
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#define CONFIG_SPL_NAND_ECC
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#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
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#define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/
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#define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */
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#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK
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/* move malloc and bss high to prevent clashing with the main image */
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#define CONFIG_SYS_SPL_MALLOC_START 0x8f000000
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#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000
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#define CONFIG_SPL_BSS_START_ADDR 0x8f080000 /* end of RAM */
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#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
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#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
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#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
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#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
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/* NAND boot config */
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#define CONFIG_SYS_NAND_PAGE_COUNT 64
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#define CONFIG_SYS_NAND_PAGE_SIZE 2048
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#define CONFIG_SYS_NAND_OOBSIZE 64
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#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
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#define CONFIG_SYS_NAND_5_ADDR_CYCLE
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#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
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#define CONFIG_SYS_NAND_ECCPOS {40, 41, 42, 43, 44, 45, 46, 47,\
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48, 49, 50, 51, 52, 53, 54, 55,\
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56, 57, 58, 59, 60, 61, 62, 63}
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#define CONFIG_SYS_NAND_ECCSIZE 256
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#define CONFIG_SYS_NAND_ECCBYTES 3
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#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_SW
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#define CONFIG_SPL_NAND_SOFTECC
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#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
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#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
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/*
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* ethernet support
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*
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*/
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#if defined(CONFIG_CMD_NET)
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#define CONFIG_DRIVER_TI_EMAC
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#define CONFIG_DRIVER_TI_EMAC_USE_RMII
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#define CONFIG_MII
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#define CONFIG_BOOTP_DNS
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#define CONFIG_BOOTP_DNS2
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#define CONFIG_BOOTP_SEND_HOSTNAME
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#define CONFIG_NET_RETRY_COUNT 10
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#endif
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#define CONFIG_VIDEO
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#define CONFIG_CFB_CONSOLE
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#define CONFIG_VGA_AS_SINGLE_DEVICE
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#define CONFIG_SPLASH_SCREEN
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#define CONFIG_VIDEO_BMP_RLE8
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#define CONFIG_CMD_BMP
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#define CONFIG_VIDEO_OMAP3
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#define CONFIG_SYS_CONSOLE_IS_IN_ENV
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#endif /* __CONFIG_H */
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