mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-14 08:57:58 +00:00
82e26e0d68
We like to put the SPL first so it is clear that it relates to SPL. Rename various malloc-related options which have crept in, to stick to this convention. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Reviewed-by: Martyn Welch <martyn.welch@collabora.com> Reviewed-by: Svyatoslav Ryhel <clamor95@gmail.com>
131 lines
3.4 KiB
Text
131 lines
3.4 KiB
Text
CONFIG_RISCV=y
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CONFIG_SYS_MALLOC_LEN=0x800000
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CONFIG_SYS_MALLOC_F_LEN=0x10000
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CONFIG_SPL_GPIO=y
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CONFIG_NR_DRAM_BANKS=1
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CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
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CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80000000
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CONFIG_SF_DEFAULT_SPEED=100000000
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CONFIG_ENV_SIZE=0x10000
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CONFIG_ENV_OFFSET=0xf0000
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CONFIG_SPL_DM_SPI=y
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CONFIG_DEFAULT_DEVICE_TREE="jh7110-starfive-visionfive-2"
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CONFIG_SPL_TEXT_BASE=0x8000000
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CONFIG_OF_LIBFDT_OVERLAY=y
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CONFIG_DM_RESET=y
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CONFIG_SPL_MMC=y
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CONFIG_SPL_DRIVERS_MISC=y
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CONFIG_SPL_STACK=0x8180000
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CONFIG_SPL=y
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CONFIG_SPL_SPI_FLASH_SUPPORT=y
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CONFIG_SPL_SPI=y
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CONFIG_SYS_LOAD_ADDR=0x82000000
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CONFIG_SYS_PCI_64BIT=y
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CONFIG_PCI=y
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CONFIG_TARGET_STARFIVE_VISIONFIVE2=y
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CONFIG_SPL_OPENSBI_LOAD_ADDR=0x40000000
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CONFIG_ARCH_RV64I=y
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CONFIG_CMODEL_MEDANY=y
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CONFIG_RISCV_SMODE=y
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# CONFIG_OF_BOARD_FIXUP is not set
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# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
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CONFIG_FIT=y
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CONFIG_DISTRO_DEFAULTS=y
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CONFIG_QSPI_BOOT=y
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CONFIG_SD_BOOT=y
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CONFIG_OF_BOARD_SETUP=y
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CONFIG_USE_BOOTARGS=y
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CONFIG_BOOTARGS="console=ttyS0,115200 debug rootwait earlycon=sbi"
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CONFIG_USE_PREBOOT=y
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CONFIG_PREBOOT="nvme scan; usb start; setenv fdt_addr ${fdtcontroladdr}; fdt addr ${fdtcontroladdr};"
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CONFIG_DEFAULT_FDT_FILE="starfive/jh7110-starfive-visionfive-2.dtb"
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CONFIG_DISPLAY_CPUINFO=y
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CONFIG_DISPLAY_BOARDINFO=y
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CONFIG_ID_EEPROM=y
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CONFIG_SYS_EEPROM_BUS_NUM=5
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CONFIG_PCI_INIT_R=y
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CONFIG_SPL_MAX_SIZE=0x40000
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CONFIG_SPL_PAD_TO=0x0
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CONFIG_SPL_BSS_START_ADDR=0x8040000
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CONFIG_SPL_BSS_MAX_SIZE=0x10000
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# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
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CONFIG_SPL_SYS_MALLOC=y
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CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
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CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x80000000
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CONFIG_SPL_SYS_MALLOC_SIZE=0x400000
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CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y
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CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=0x2
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CONFIG_SPL_I2C=y
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CONFIG_SPL_DM_SPI_FLASH=y
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CONFIG_SPL_DM_RESET=y
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CONFIG_SPL_SPI_LOAD=y
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CONFIG_SYS_PROMPT="StarFive # "
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CONFIG_SYS_CBSIZE=256
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CONFIG_SYS_PBSIZE=276
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CONFIG_SYS_BOOTM_LEN=0x4000000
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CONFIG_CMD_EEPROM=y
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CONFIG_SYS_EEPROM_SIZE=512
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CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=4
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CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
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CONFIG_CMD_MEMINFO=y
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CONFIG_CMD_I2C=y
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CONFIG_CMD_PCI=y
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CONFIG_CMD_USB=y
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CONFIG_CMD_TFTPPUT=y
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CONFIG_OF_BOARD=y
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CONFIG_ENV_OVERWRITE=y
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CONFIG_ENV_IS_NOWHERE=y
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CONFIG_ENV_IS_IN_SPI_FLASH=y
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CONFIG_ENV_SECT_SIZE_AUTO=y
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CONFIG_SYS_RELOC_GD_ENV_ADDR=y
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CONFIG_SPL_DM_SEQ_ALIAS=y
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CONFIG_REGMAP=y
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CONFIG_SYSCON=y
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CONFIG_SPL_CLK_COMPOSITE_CCF=y
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CONFIG_CLK_COMPOSITE_CCF=y
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CONFIG_SPL_CLK_JH7110=y
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CONFIG_DM_I2C=y
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CONFIG_SYS_I2C_DW=y
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CONFIG_MISC=y
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CONFIG_I2C_EEPROM=y
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CONFIG_SPL_I2C_EEPROM=y
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CONFIG_SYS_I2C_EEPROM_ADDR=0X50
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CONFIG_MMC_HS400_SUPPORT=y
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CONFIG_SPL_MMC_HS400_SUPPORT=y
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CONFIG_MMC_DW=y
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CONFIG_MMC_DW_SNPS=y
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CONFIG_SPI_FLASH_EON=y
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CONFIG_SPI_FLASH_GIGADEVICE=y
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CONFIG_SPI_FLASH_ISSI=y
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CONFIG_SPI_FLASH_MACRONIX=y
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CONFIG_PHY_MOTORCOMM=y
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CONFIG_DM_MDIO=y
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CONFIG_DM_ETH_PHY=y
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CONFIG_DWC_ETH_QOS=y
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CONFIG_DWC_ETH_QOS_STARFIVE=y
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CONFIG_RGMII=y
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CONFIG_RMII=y
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CONFIG_RTL8169=y
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CONFIG_NVME_PCI=y
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CONFIG_DM_PCI_COMPAT=y
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CONFIG_PCI_REGION_MULTI_ENTRY=y
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CONFIG_PCIE_STARFIVE_JH7110=y
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CONFIG_PINCTRL=y
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CONFIG_PINCONF=y
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CONFIG_SPL_PINCTRL=y
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CONFIG_SPL_PINCONF=y
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CONFIG_SPL_PINCTRL_STARFIVE=y
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CONFIG_SPL_PINCTRL_STARFIVE_JH7110=y
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CONFIG_PINCTRL_STARFIVE=y
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# CONFIG_RAM_SIFIVE is not set
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CONFIG_SYS_NS16550=y
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CONFIG_CADENCE_QSPI=y
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CONFIG_TIMER_EARLY=y
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CONFIG_USB=y
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CONFIG_USB_XHCI_HCD=y
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CONFIG_USB_XHCI_PCI=y
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CONFIG_USB_EHCI_HCD=y
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CONFIG_USB_EHCI_PCI=y
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CONFIG_USB_OHCI_HCD=y
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CONFIG_USB_OHCI_PCI=y
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CONFIG_USB_KEYBOARD=y
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