mirror of
https://github.com/AsahiLinux/u-boot
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65cc0e2a65
The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
161 lines
4 KiB
C
161 lines
4 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
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*
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* Based on davinci_dvevm.h. Original Copyrights follow:
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*
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* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* Board
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*/
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/*
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* SoC Configuration
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*/
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#define CFG_SYS_OSCIN_FREQ 24000000
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#define CFG_SYS_TIMERBASE DAVINCI_TIMER0_BASE
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#define CFG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID)
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/*
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* Memory Info
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*/
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#define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */
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#define PHYS_SDRAM_1_SIZE (128 << 20) /* SDRAM size 128MB */
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#define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/
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/* memtest start addr */
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/* memtest will be run on 16MB */
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#define CFG_SYS_DA850_SYSCFG_SUSPSRC ( \
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DAVINCI_SYSCFG_SUSPSRC_TIMER0 | \
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DAVINCI_SYSCFG_SUSPSRC_SPI1 | \
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DAVINCI_SYSCFG_SUSPSRC_UART2 | \
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DAVINCI_SYSCFG_SUSPSRC_EMAC | \
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DAVINCI_SYSCFG_SUSPSRC_I2C)
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/*
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* PLL configuration
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*/
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/* Requires CONFIG_SYS_DA850_PLL0_POSTDIV=0, set in Kconfig */
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#define CFG_SYS_DA850_PLL0_PLLM 18
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#define CFG_SYS_DA850_PLL1_PLLM 21
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/*
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* DDR2 memory configuration
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*/
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#define CFG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \
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DV_DDR_PHY_EXT_STRBEN | \
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(0x5 << DV_DDR_PHY_RD_LATENCY_SHIFT))
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#define CFG_SYS_DA850_DDR2_SDBCR ( \
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(1 << DV_DDR_SDCR_DDR2EN_SHIFT) | \
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(1 << DV_DDR_SDCR_DDREN_SHIFT) | \
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(1 << DV_DDR_SDCR_SDRAMEN_SHIFT) | \
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(1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) | \
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(4 << DV_DDR_SDCR_CL_SHIFT) | \
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(3 << DV_DDR_SDCR_IBANK_SHIFT) | \
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(2 << DV_DDR_SDCR_PAGESIZE_SHIFT))
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/* SDBCR2 is only used if IBANK_POS bit in SDBCR is set */
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#define CFG_SYS_DA850_DDR2_SDBCR2 0
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#define CFG_SYS_DA850_DDR2_SDTIMR ( \
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(19 << DV_DDR_SDTMR1_RFC_SHIFT) | \
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(1 << DV_DDR_SDTMR1_RP_SHIFT) | \
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(1 << DV_DDR_SDTMR1_RCD_SHIFT) | \
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(2 << DV_DDR_SDTMR1_WR_SHIFT) | \
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(6 << DV_DDR_SDTMR1_RAS_SHIFT) | \
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(8 << DV_DDR_SDTMR1_RC_SHIFT) | \
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(1 << DV_DDR_SDTMR1_RRD_SHIFT) | \
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(1 << DV_DDR_SDTMR1_WTR_SHIFT))
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#define CFG_SYS_DA850_DDR2_SDTIMR2 ( \
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(7 << DV_DDR_SDTMR2_RASMAX_SHIFT) | \
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(2 << DV_DDR_SDTMR2_XP_SHIFT) | \
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(0 << DV_DDR_SDTMR2_ODT_SHIFT) | \
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(20 << DV_DDR_SDTMR2_XSNR_SHIFT) | \
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(199 << DV_DDR_SDTMR2_XSRD_SHIFT) | \
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(1 << DV_DDR_SDTMR2_RTP_SHIFT) | \
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(2 << DV_DDR_SDTMR2_CKE_SHIFT))
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#define CFG_SYS_DA850_DDR2_SDRCR 0x00000492
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#define CFG_SYS_DA850_DDR2_PBBPR 0x30
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/*
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* Serial Driver info
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*/
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#define CFG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID)
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#define CFG_SYS_SPI_BASE DAVINCI_SPI1_BASE
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#define CFG_SYS_SPI_CLK clk_get(DAVINCI_SPI1_CLKID)
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/*
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* I2C Configuration
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*/
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#define CFG_SYS_I2C_EXPANDER_ADDR 0x20
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/*
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* Flash & Environment
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*/
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#ifdef CONFIG_MTD_RAW_NAND
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#define CFG_SYS_NAND_CS 3
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#define CFG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
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#define CFG_SYS_NAND_MASK_CLE 0x10
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#define CFG_SYS_NAND_MASK_ALE 0x8
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#define CONFIG_NAND_6BYTES_OOB_FREE_10BYTES_ECC
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#define CFG_SYS_NAND_U_BOOT_SIZE SZ_512K
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#define CFG_SYS_NAND_U_BOOT_DST 0xc1080000
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#define CFG_SYS_NAND_U_BOOT_START CFG_SYS_NAND_U_BOOT_DST
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#define CFG_SYS_NAND_ECCPOS { \
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6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
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22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \
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38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
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54, 55, 56, 57, 58, 59, 60, 61, 62, 63 }
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#define CFG_SYS_NAND_ECCSIZE 512
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#define CFG_SYS_NAND_ECCBYTES 10
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#endif
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/*
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* U-Boot general configuration
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*/
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/*
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* Linux Information
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*/
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#define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100)
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#define DEFAULT_LINUX_BOOT_ENV \
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"loadaddr=0xc0700000\0" \
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"fdtaddr=0xc0600000\0" \
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"scriptaddr=0xc0600000\0"
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#include <environment/ti/mmc.h>
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#define CONFIG_EXTRA_ENV_SETTINGS \
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DEFAULT_LINUX_BOOT_ENV \
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DEFAULT_MMC_TI_ARGS \
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"bootpart=0:2\0" \
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"bootdir=/boot\0" \
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"bootfile=zImage\0" \
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"fdtfile=da850-lcdk.dtb\0" \
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"boot_fdt=yes\0" \
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"boot_fit=0\0" \
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"console=ttyS2,115200n8\0"
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/* SD/MMC */
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/* defines for SPL */
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/* additions for new relocation code, must added to all boards */
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#define CFG_SYS_SDRAM_BASE 0xc0000000
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#include <asm/arch/hardware.h>
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#endif /* __CONFIG_H */
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