mirror of
https://github.com/AsahiLinux/u-boot
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91caa3bb89
Add a new event which handles this function. Convert existing use of the function to use the new event instead. Make sure that EVENT is enabled by affected boards, by selecting it from the LAST_STAGE_INIT option. For x86, enable it by default since all boards need it. For controlcenterdc, inline the get_tpm() function and make sure the event is not built in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
334 lines
8.9 KiB
C
334 lines
8.9 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2006 Freescale Semiconductor, Inc.
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* Dave Liu <daveliu@freescale.com>
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*
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* Copyright (C) 2007 Logic Product Development, Inc.
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* Peter Barada <peterb@logicpd.com>
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*
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* Copyright (C) 2007 MontaVista Software, Inc.
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* Anton Vorontsov <avorontsov@ru.mvista.com>
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*
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* (C) Copyright 2008 - 2010
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* Heiko Schocher, DENX Software Engineering, hs@denx.de.
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*/
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#include <common.h>
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#include <env.h>
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#include <event.h>
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#include <fdt_support.h>
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#include <init.h>
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#include <ioports.h>
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#include <log.h>
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#include <mpc83xx.h>
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#include <i2c.h>
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#include <miiphy.h>
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#include <asm/global_data.h>
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#include <asm/io.h>
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#include <asm/mmu.h>
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#include <asm/processor.h>
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#include <pci.h>
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#include <linux/delay.h>
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#include <linux/libfdt.h>
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#include <post.h>
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#include "../common/common.h"
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DECLARE_GLOBAL_DATA_PTR;
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#if CONFIG_IS_ENABLED(TARGET_KMCOGE5NE) || CONFIG_IS_ENABLED(TARGET_KMETER1)
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#define CFG_SYS_DDR_MODE 0x47860452
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#define CFG_SYS_DDR_INTERVAL (\
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(0x080 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
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(0x203 << SDRAM_INTERVAL_REFINT_SHIFT))
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#define CFG_SYS_DDR_TIMING_0 (\
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(2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
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(8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
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(6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
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(2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
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(0 << TIMING_CFG0_WWT_SHIFT) | \
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(0 << TIMING_CFG0_RRT_SHIFT) | \
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(0 << TIMING_CFG0_WRT_SHIFT) | \
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(0 << TIMING_CFG0_RWT_SHIFT))
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#define CFG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_50) | \
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(2 << TIMING_CFG1_WRTORD_SHIFT) | \
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(2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
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(3 << TIMING_CFG1_WRREC_SHIFT) | \
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(7 << TIMING_CFG1_REFREC_SHIFT) | \
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(3 << TIMING_CFG1_ACTTORW_SHIFT) | \
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(8 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
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(3 << TIMING_CFG1_PRETOACT_SHIFT))
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#define CFG_SYS_DDR_TIMING_2 (\
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(0xa << TIMING_CFG2_FOUR_ACT_SHIFT) | \
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(3 << TIMING_CFG2_CKE_PLS_SHIFT) | \
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(2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
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(2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
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(4 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
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(5 << TIMING_CFG2_CPO_SHIFT) | \
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(0 << TIMING_CFG2_ADD_LAT_SHIFT))
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#define CFG_SYS_DDR_TIMING_3 0x00000000
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#else
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#define CFG_SYS_DDR_MODE 0x47860242
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#define CFG_SYS_DDR_INTERVAL ((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
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(0x200 << SDRAM_INTERVAL_REFINT_SHIFT))
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#define CFG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
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(8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
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(2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
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(2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
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(0 << TIMING_CFG0_WWT_SHIFT) | \
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(0 << TIMING_CFG0_RRT_SHIFT) | \
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(0 << TIMING_CFG0_WRT_SHIFT) | \
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(0 << TIMING_CFG0_RWT_SHIFT))
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#define CFG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_40) | \
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(2 << TIMING_CFG1_WRTORD_SHIFT) | \
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(2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
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(3 << TIMING_CFG1_WRREC_SHIFT) | \
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(7 << TIMING_CFG1_REFREC_SHIFT) | \
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(3 << TIMING_CFG1_ACTTORW_SHIFT) | \
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(7 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
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(3 << TIMING_CFG1_PRETOACT_SHIFT))
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#define CFG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \
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(3 << TIMING_CFG2_CKE_PLS_SHIFT) | \
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(2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
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(2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
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(3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
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(0 << TIMING_CFG2_ADD_LAT_SHIFT) | \
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(5 << TIMING_CFG2_CPO_SHIFT))
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#define CFG_SYS_DDR_TIMING_3 0x00000000
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#define CFG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \
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CSCONFIG_ODT_WR_CFG | \
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CSCONFIG_ROW_BIT_13 | \
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CSCONFIG_COL_BIT_10)
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#endif
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#define CFG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 | \
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SDRAM_CFG_32_BE | \
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SDRAM_CFG_SREN | \
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SDRAM_CFG_HSE)
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#define CFG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
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#define CFG_SYS_DDR_SDRAM_CFG2 0x00401000
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#define CFG_SYS_DDR_CS0_BNDS 0x0000007f
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#define CFG_SYS_DDR_MODE2 0x8080c000
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#define CFG_SYS_SDRAM_SIZE 0x80000000 /* 2048 MiB */
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static uchar ivm_content[CONFIG_SYS_IVM_EEPROM_MAX_LEN];
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static int piggy_present(void)
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{
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struct km_bec_fpga __iomem *base =
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(struct km_bec_fpga __iomem *)CFG_SYS_KMBEC_FPGA_BASE;
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return in_8(&base->bprth) & PIGGY_PRESENT;
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}
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int ethernet_present(void)
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{
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return piggy_present();
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}
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int board_early_init_r(void)
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{
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struct km_bec_fpga *base =
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(struct km_bec_fpga *)CFG_SYS_KMBEC_FPGA_BASE;
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#if defined(CONFIG_ARCH_MPC8360)
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unsigned short svid;
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/*
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* Because of errata in the UCCs, we have to write to the reserved
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* registers to slow the clocks down.
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*/
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svid = SVR_REV(mfspr(SVR));
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switch (svid) {
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case 0x0020:
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/*
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* MPC8360ECE.pdf QE_ENET10 table 4:
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* IMMR + 0x14A8[4:5] = 11 (clk delay for UCC 2)
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* IMMR + 0x14A8[18:19] = 11 (clk delay for UCC 1)
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*/
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setbits_be32((void *)(CONFIG_SYS_IMMR + 0x14a8), 0x0c003000);
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break;
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case 0x0021:
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/*
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* MPC8360ECE.pdf QE_ENET10 table 4:
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* IMMR + 0x14AC[24:27] = 1010
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*/
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clrsetbits_be32((void *)(CONFIG_SYS_IMMR + 0x14ac),
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0x00000050, 0x000000a0);
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break;
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}
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#endif
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/* enable the PHY on the PIGGY */
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setbits_8(&base->pgy_eth, 0x01);
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/* enable the Unit LED (green) */
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setbits_8(&base->oprth, WRL_BOOT);
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/* enable Application Buffer */
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setbits_8(&base->oprtl, OPRTL_XBUFENA);
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return 0;
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}
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int misc_init_r(void)
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{
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ivm_read_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN,
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CONFIG_PIGGY_MAC_ADDRESS_OFFSET);
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return 0;
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}
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static int last_stage_init(void)
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{
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#if defined(CONFIG_TARGET_KMCOGE5NE)
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/*
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* BFTIC3 on the local bus CS4
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*/
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struct bfticu_iomap *base = (struct bfticu_iomap *)0xB0000000;
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u8 dip_switch = in_8((u8 *)&(base->mswitch)) & BFTICU_DIPSWITCH_MASK;
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if (dip_switch != 0) {
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/* start bootloader */
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puts("DIP: Enabled\n");
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env_set("actual_bank", "0");
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}
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#endif
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set_km_env();
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return 0;
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}
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EVENT_SPY_SIMPLE(EVT_LAST_STAGE_INIT, last_stage_init);
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static int fixed_sdram(void)
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{
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immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
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u32 msize = 0;
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u32 ddr_size;
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u32 ddr_size_log2;
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out_be32(&im->sysconf.ddrlaw[0].ar, (LAWAR_EN | 0x1e));
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out_be32(&im->ddr.csbnds[0].csbnds, (CFG_SYS_DDR_CS0_BNDS) | 0x7f);
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out_be32(&im->ddr.cs_config[0], CFG_SYS_DDR_CS0_CONFIG);
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out_be32(&im->ddr.timing_cfg_0, CFG_SYS_DDR_TIMING_0);
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out_be32(&im->ddr.timing_cfg_1, CFG_SYS_DDR_TIMING_1);
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out_be32(&im->ddr.timing_cfg_2, CFG_SYS_DDR_TIMING_2);
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out_be32(&im->ddr.timing_cfg_3, CFG_SYS_DDR_TIMING_3);
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out_be32(&im->ddr.sdram_cfg, CFG_SYS_DDR_SDRAM_CFG);
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out_be32(&im->ddr.sdram_cfg2, CFG_SYS_DDR_SDRAM_CFG2);
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out_be32(&im->ddr.sdram_mode, CFG_SYS_DDR_MODE);
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out_be32(&im->ddr.sdram_mode2, CFG_SYS_DDR_MODE2);
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out_be32(&im->ddr.sdram_interval, CFG_SYS_DDR_INTERVAL);
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out_be32(&im->ddr.sdram_clk_cntl, CFG_SYS_DDR_CLK_CNTL);
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udelay(200);
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setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN);
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disable_addr_trans();
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msize = get_ram_size(CFG_SYS_SDRAM_BASE, CFG_SYS_SDRAM_SIZE);
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enable_addr_trans();
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msize /= (1024 * 1024);
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if (CFG_SYS_SDRAM_SIZE >> 20 != msize) {
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for (ddr_size = msize << 20, ddr_size_log2 = 0;
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(ddr_size > 1);
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ddr_size = ddr_size >> 1, ddr_size_log2++)
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if (ddr_size & 1)
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return -1;
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out_be32(&im->sysconf.ddrlaw[0].ar,
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(LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE)));
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out_be32(&im->ddr.csbnds[0].csbnds,
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(((msize / 16) - 1) & 0xff));
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}
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return msize;
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}
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int dram_init(void)
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{
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immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
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u32 msize = 0;
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if ((in_be32(&im->sysconf.immrbar) & IMMRBAR_BASE_ADDR) != (u32)im)
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return -ENXIO;
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out_be32(&im->sysconf.ddrlaw[0].bar,
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CFG_SYS_SDRAM_BASE & LAWBAR_BAR);
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msize = fixed_sdram();
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#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
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/*
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* Initialize DDR ECC byte
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*/
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ddr_enable_ecc(msize * 1024 * 1024);
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#endif
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/* return total bus SDRAM size(bytes) -- DDR */
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gd->ram_size = msize * 1024 * 1024;
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return 0;
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}
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int checkboard(void)
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{
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puts("Board: Hitachi " CONFIG_SYS_CONFIG_NAME);
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if (piggy_present())
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puts(" with PIGGY.");
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puts("\n");
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return 0;
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}
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int ft_board_setup(void *blob, struct bd_info *bd)
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{
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ft_cpu_setup(blob, bd);
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return 0;
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}
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#if defined(CONFIG_HUSH_INIT_VAR)
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int hush_init_var(void)
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{
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ivm_analyze_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN);
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return 0;
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}
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#endif
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#if defined(CONFIG_POST)
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int post_hotkeys_pressed(void)
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{
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int testpin = 0;
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struct km_bec_fpga *base =
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(struct km_bec_fpga *)CFG_SYS_KMBEC_FPGA_BASE;
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int testpin_reg = in_8(&base->CFG_TESTPIN_REG);
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testpin = (testpin_reg & CFG_TESTPIN_MASK) != 0;
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debug("post_hotkeys_pressed: %d\n", !testpin);
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return testpin;
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}
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ulong post_word_load(void)
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{
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void* addr = (ulong *) (CPM_POST_WORD_ADDR);
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debug("post_word_load 0x%08lX: 0x%08X\n", (ulong)addr, in_le32(addr));
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return in_le32(addr);
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}
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void post_word_store(ulong value)
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{
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void* addr = (ulong *) (CPM_POST_WORD_ADDR);
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debug("post_word_store 0x%08lX: 0x%08lX\n", (ulong)addr, value);
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out_le32(addr, value);
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}
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int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
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{
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*vstart = CONFIG_SYS_MEMTEST_START;
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*size = CONFIG_SYS_MEMTEST_END - CONFIG_SYS_MEMTEST_START;
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debug("arch_memory_test_prepare 0x%08X 0x%08X\n", *vstart, *size);
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return 0;
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}
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#endif
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