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https://github.com/AsahiLinux/u-boot
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e479a7d52e
This introduces initial support for the popular Qualcomm IPQ40x8 and IPQ40x9 WiSoC series. IPQ40xx series have 4x Cortex A7 ARM-v7A cores. Supported are: IPQ4018, IPQ4019, IPQ4028 and IPQ4029. IPQ40x8 and IPQ40x9 use the same cores, but differ in addressable RAM size (1GB for IPQ40x9 and 256MB for IPQ40x8) and supported peripherals (IPQ40x8 lacks RGMII, LCD controller and EMMC/SDHCI controllers). IQP4028/IPQ4029 models differ from IPQ4018/IPQ4019 only by their rated temperatures rates with IPQ402X models being rated for wider temperature ranges. Initially this supports: * Simple clock driver (Only for UART1 now, will be extended) * Pinctrl driver (Supports UARTX and GPIO now, will be extended) * GPIOs already supported by msm_gpio driver with updates * UARTs already supported by serial_msm driver with updates Further peripherals will come in later patches. Signed-off-by: Robert Marko <robert.marko@sartura.hr>
79 lines
1.5 KiB
Text
79 lines
1.5 KiB
Text
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (c) 2019 Sartura Ltd.
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*
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* Author: Robert Marko <robert.marko@sartura.hr>
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*/
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/dts-v1/;
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#include "skeleton.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/pinctrl/pinctrl-snapdragon.h>
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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model = "Qualcomm Technologies, Inc. IPQ4019";
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compatible = "qcom,ipq4019";
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aliases {
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serial0 = &blsp1_uart1;
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};
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reserved-memory {
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#address-cells = <0x1>;
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#size-cells = <0x1>;
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ranges;
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smem_mem: smem_region: smem@87e00000 {
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reg = <0x87e00000 0x080000>;
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no-map;
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};
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tz@87e80000 {
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reg = <0x87e80000 0x180000>;
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no-map;
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};
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};
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soc: soc {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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compatible = "simple-bus";
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gcc: clock-controller@1800000 {
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compatible = "qcom,gcc-ipq4019";
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reg = <0x1800000 0x60000>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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u-boot,dm-pre-reloc;
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};
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pinctrl: qcom,tlmm@1000000 {
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compatible = "qcom,tlmm-ipq4019";
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reg = <0x1000000 0x300000>;
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u-boot,dm-pre-reloc;
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};
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blsp1_uart1: serial@78af000 {
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compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
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reg = <0x78af000 0x200>;
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clock = <&gcc 26>;
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bit-rate = <0xFF>;
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status = "disabled";
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u-boot,dm-pre-reloc;
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};
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soc_gpios: pinctrl@1000000 {
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compatible = "qcom,ipq4019-pinctrl";
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reg = <0x1000000 0x300000>;
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gpio-controller;
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gpio-count = <100>;
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gpio-bank-name="soc";
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#gpio-cells = <2>;
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};
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};
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};
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