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918e9c3d63
Move function board_ddr_power_init() in a new file stpmic1 in board/st/common to avoid duplicated code in each board using stpmic1 Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
164 lines
3.7 KiB
C
164 lines
3.7 KiB
C
// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
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/*
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* Copyright (C) 2020, STMicroelectronics - All Rights Reserved
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*/
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#include <common.h>
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#include <dm.h>
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#include <asm/arch/ddr.h>
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#include <linux/bitops.h>
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#include <linux/delay.h>
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#include <power/pmic.h>
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#include <power/stpmic1.h>
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int board_ddr_power_init(enum ddr_type ddr_type)
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{
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struct udevice *dev;
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bool buck3_at_1800000v = false;
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int ret;
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u32 buck2;
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ret = uclass_get_device_by_driver(UCLASS_PMIC,
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DM_GET_DRIVER(pmic_stpmic1), &dev);
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if (ret)
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/* No PMIC on board */
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return 0;
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switch (ddr_type) {
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case STM32MP_DDR3:
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/* VTT = Set LDO3 to sync mode */
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ret = pmic_reg_read(dev, STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3));
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if (ret < 0)
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return ret;
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ret &= ~STPMIC1_LDO3_MODE;
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ret &= ~STPMIC1_LDO12356_VOUT_MASK;
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ret |= STPMIC1_LDO_VOUT(STPMIC1_LDO3_DDR_SEL);
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ret = pmic_reg_write(dev, STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3),
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ret);
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if (ret < 0)
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return ret;
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/* VDD_DDR = Set BUCK2 to 1.35V */
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ret = pmic_clrsetbits(dev,
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STPMIC1_BUCKX_MAIN_CR(STPMIC1_BUCK2),
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STPMIC1_BUCK_VOUT_MASK,
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STPMIC1_BUCK2_1350000V);
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if (ret < 0)
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return ret;
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/* Enable VDD_DDR = BUCK2 */
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ret = pmic_clrsetbits(dev,
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STPMIC1_BUCKX_MAIN_CR(STPMIC1_BUCK2),
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STPMIC1_BUCK_ENA, STPMIC1_BUCK_ENA);
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if (ret < 0)
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return ret;
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mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS);
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/* Enable VREF */
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ret = pmic_clrsetbits(dev, STPMIC1_REFDDR_MAIN_CR,
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STPMIC1_VREF_ENA, STPMIC1_VREF_ENA);
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if (ret < 0)
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return ret;
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mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS);
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/* Enable VTT = LDO3 */
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ret = pmic_clrsetbits(dev,
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STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3),
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STPMIC1_LDO_ENA, STPMIC1_LDO_ENA);
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if (ret < 0)
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return ret;
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mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS);
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break;
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case STM32MP_LPDDR2_16:
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case STM32MP_LPDDR2_32:
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case STM32MP_LPDDR3_16:
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case STM32MP_LPDDR3_32:
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/*
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* configure VDD_DDR1 = LDO3
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* Set LDO3 to 1.8V
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* + bypass mode if BUCK3 = 1.8V
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* + normal mode if BUCK3 != 1.8V
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*/
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ret = pmic_reg_read(dev,
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STPMIC1_BUCKX_MAIN_CR(STPMIC1_BUCK3));
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if (ret < 0)
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return ret;
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if ((ret & STPMIC1_BUCK3_1800000V) == STPMIC1_BUCK3_1800000V)
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buck3_at_1800000v = true;
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ret = pmic_reg_read(dev, STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3));
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if (ret < 0)
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return ret;
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ret &= ~STPMIC1_LDO3_MODE;
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ret &= ~STPMIC1_LDO12356_VOUT_MASK;
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ret |= STPMIC1_LDO3_1800000;
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if (buck3_at_1800000v)
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ret |= STPMIC1_LDO3_MODE;
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ret = pmic_reg_write(dev, STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3),
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ret);
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if (ret < 0)
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return ret;
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/* VDD_DDR2 : Set BUCK2 to 1.2V (16bits) or 1.25V (32 bits)*/
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switch (ddr_type) {
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case STM32MP_LPDDR2_32:
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case STM32MP_LPDDR3_32:
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buck2 = STPMIC1_BUCK2_1250000V;
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break;
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default:
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case STM32MP_LPDDR2_16:
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case STM32MP_LPDDR3_16:
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buck2 = STPMIC1_BUCK2_1200000V;
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break;
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}
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ret = pmic_clrsetbits(dev,
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STPMIC1_BUCKX_MAIN_CR(STPMIC1_BUCK2),
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STPMIC1_BUCK_VOUT_MASK,
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buck2);
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if (ret < 0)
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return ret;
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/* Enable VDD_DDR1 = LDO3 */
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ret = pmic_clrsetbits(dev, STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3),
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STPMIC1_LDO_ENA, STPMIC1_LDO_ENA);
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if (ret < 0)
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return ret;
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mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS);
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/* Enable VDD_DDR2 =BUCK2 */
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ret = pmic_clrsetbits(dev,
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STPMIC1_BUCKX_MAIN_CR(STPMIC1_BUCK2),
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STPMIC1_BUCK_ENA, STPMIC1_BUCK_ENA);
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if (ret < 0)
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return ret;
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mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS);
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/* Enable VREF */
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ret = pmic_clrsetbits(dev, STPMIC1_REFDDR_MAIN_CR,
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STPMIC1_VREF_ENA, STPMIC1_VREF_ENA);
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if (ret < 0)
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return ret;
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mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS);
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break;
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default:
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break;
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};
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return 0;
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}
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