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https://github.com/AsahiLinux/u-boot
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f09f1ecbe7
Some places use __ASSEMBLER__ instead which does not work since the Makefile does not define it. Fix them. Signed-off-by: Simon Glass <sjg@chromium.org>
328 lines
11 KiB
C
328 lines
11 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2013-2016, Freescale Semiconductor, Inc.
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*/
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#ifndef __ASM_ARCH_IMX_REGS_H__
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#define __ASM_ARCH_IMX_REGS_H__
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#define ARCH_MXC
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#define IRAM_BASE_ADDR 0x3E800000 /* internal ram */
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#define IRAM_SIZE 0x00400000 /* 4MB */
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#define AIPS0_BASE_ADDR (0x40000000UL)
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#define AIPS1_BASE_ADDR (0x40080000UL)
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/* AIPS 0 */
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#define AXBS_BASE_ADDR (AIPS0_BASE_ADDR + 0x00000000)
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#define CSE3_BASE_ADDR (AIPS0_BASE_ADDR + 0x00001000)
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#define EDMA_BASE_ADDR (AIPS0_BASE_ADDR + 0x00002000)
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#define XRDC_BASE_ADDR (AIPS0_BASE_ADDR + 0x00004000)
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#define SWT0_BASE_ADDR (AIPS0_BASE_ADDR + 0x0000A000)
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#define SWT1_BASE_ADDR (AIPS0_BASE_ADDR + 0x0000B000)
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#define STM0_BASE_ADDR (AIPS0_BASE_ADDR + 0x0000D000)
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#define NIC301_BASE_ADDR (AIPS0_BASE_ADDR + 0x00010000)
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#define GC3000_BASE_ADDR (AIPS0_BASE_ADDR + 0x00020000)
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#define DEC200_DECODER_BASE_ADDR (AIPS0_BASE_ADDR + 0x00026000)
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#define DEC200_ENCODER_BASE_ADDR (AIPS0_BASE_ADDR + 0x00027000)
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#define TWOD_ACE_BASE_ADDR (AIPS0_BASE_ADDR + 0x00028000)
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#define MIPI_CSI0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00030000)
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#define DMAMUX0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00031000)
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#define ENET_BASE_ADDR (AIPS0_BASE_ADDR + 0x00032000)
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#define FLEXRAY_BASE_ADDR (AIPS0_BASE_ADDR + 0x00034000)
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#define MMDC0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00036000)
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#define MEW0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00037000)
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#define MONITOR_DDR0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00038000)
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#define MONITOR_CCI0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00039000)
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#define PIT0_BASE_ADDR (AIPS0_BASE_ADDR + 0x0003A000)
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#define MC_CGM0_BASE_ADDR (AIPS0_BASE_ADDR + 0x0003C000)
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#define MC_CGM1_BASE_ADDR (AIPS0_BASE_ADDR + 0x0003F000)
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#define MC_CGM2_BASE_ADDR (AIPS0_BASE_ADDR + 0x00042000)
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#define MC_CGM3_BASE_ADDR (AIPS0_BASE_ADDR + 0x00045000)
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#define MC_RGM_BASE_ADDR (AIPS0_BASE_ADDR + 0x00048000)
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#define MC_ME_BASE_ADDR (AIPS0_BASE_ADDR + 0x0004A000)
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#define MC_PCU_BASE_ADDR (AIPS0_BASE_ADDR + 0x0004B000)
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#define ADC0_BASE_ADDR (AIPS0_BASE_ADDR + 0x0004D000)
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#define FLEXTIMER_BASE_ADDR (AIPS0_BASE_ADDR + 0x0004F000)
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#define I2C0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00051000)
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#define LINFLEXD0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00053000)
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#define FLEXCAN0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00055000)
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#define SPI0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00057000)
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#define SPI2_BASE_ADDR (AIPS0_BASE_ADDR + 0x00059000)
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#define CRC0_BASE_ADDR (AIPS0_BASE_ADDR + 0x0005B000)
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#define USDHC_BASE_ADDR (AIPS0_BASE_ADDR + 0x0005D000)
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#define OCOTP_CONTROLLER_BASE_ADDR (AIPS0_BASE_ADDR + 0x0005F000)
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#define WKPU_BASE_ADDR (AIPS0_BASE_ADDR + 0x00063000)
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#define VIU0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00064000)
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#define HPSMI_SRAM_CONTROLLER_BASE_ADDR (AIPS0_BASE_ADDR + 0x00068000)
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#define SIUL2_BASE_ADDR (AIPS0_BASE_ADDR + 0x0006C000)
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#define SIPI_BASE_ADDR (AIPS0_BASE_ADDR + 0x00074000)
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#define LFAST_BASE_ADDR (AIPS0_BASE_ADDR + 0x00078000)
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#define SSE_BASE_ADDR (AIPS0_BASE_ADDR + 0x00079000)
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#define SRC_SOC_BASE_ADDR (AIPS0_BASE_ADDR + 0x0007C000)
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/* AIPS 1 */
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#define ERM_BASE_ADDR (AIPS1_BASE_ADDR + 0X000000000)
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#define MSCM_BASE_ADDR (AIPS1_BASE_ADDR + 0X000001000)
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#define SEMA42_BASE_ADDR (AIPS1_BASE_ADDR + 0X000002000)
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#define INTC_MON_BASE_ADDR (AIPS1_BASE_ADDR + 0X000003000)
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#define SWT2_BASE_ADDR (AIPS1_BASE_ADDR + 0X000004000)
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#define SWT3_BASE_ADDR (AIPS1_BASE_ADDR + 0X000005000)
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#define SWT4_BASE_ADDR (AIPS1_BASE_ADDR + 0X000006000)
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#define STM1_BASE_ADDR (AIPS1_BASE_ADDR + 0X000007000)
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#define EIM_BASE_ADDR (AIPS1_BASE_ADDR + 0X000008000)
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#define APB_BASE_ADDR (AIPS1_BASE_ADDR + 0X000009000)
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#define XBIC_BASE_ADDR (AIPS1_BASE_ADDR + 0X000012000)
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#define MIPI_BASE_ADDR (AIPS1_BASE_ADDR + 0X000020000)
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#define DMAMUX1_BASE_ADDR (AIPS1_BASE_ADDR + 0X000021000)
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#define MMDC1_BASE_ADDR (AIPS1_BASE_ADDR + 0X000022000)
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#define MEW1_BASE_ADDR (AIPS1_BASE_ADDR + 0X000023000)
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#define DDR1_BASE_ADDR (AIPS1_BASE_ADDR + 0X000024000)
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#define CCI1_BASE_ADDR (AIPS1_BASE_ADDR + 0X000025000)
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#define QUADSPI0_BASE_ADDR (AIPS1_BASE_ADDR + 0X000026000)
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#define PIT1_BASE_ADDR (AIPS1_BASE_ADDR + 0X00002A000)
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#define FCCU_BASE_ADDR (AIPS1_BASE_ADDR + 0X000030000)
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#define FLEXTIMER_FTM1_BASE_ADDR (AIPS1_BASE_ADDR + 0X000036000)
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#define I2C1_BASE_ADDR (AIPS1_BASE_ADDR + 0X000038000)
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#define I2C2_BASE_ADDR (AIPS1_BASE_ADDR + 0X00003A000)
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#define LINFLEXD1_BASE_ADDR (AIPS1_BASE_ADDR + 0X00003C000)
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#define FLEXCAN1_BASE_ADDR (AIPS1_BASE_ADDR + 0X00003E000)
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#define SPI1_BASE_ADDR (AIPS1_BASE_ADDR + 0X000040000)
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#define SPI3_BASE_ADDR (AIPS1_BASE_ADDR + 0X000042000)
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#define IPL_BASE_ADDR (AIPS1_BASE_ADDR + 0X000043000)
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#define CGM_CMU_BASE_ADDR (AIPS1_BASE_ADDR + 0X000044000)
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#define PMC_BASE_ADDR (AIPS1_BASE_ADDR + 0X000048000)
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#define CRC1_BASE_ADDR (AIPS1_BASE_ADDR + 0X00004C000)
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#define TMU_BASE_ADDR (AIPS1_BASE_ADDR + 0X00004E000)
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#define VIU1_BASE_ADDR (AIPS1_BASE_ADDR + 0X000050000)
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#define JPEG_BASE_ADDR (AIPS1_BASE_ADDR + 0X000054000)
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#define H264_DEC_BASE_ADDR (AIPS1_BASE_ADDR + 0X000058000)
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#define H264_ENC_BASE_ADDR (AIPS1_BASE_ADDR + 0X00005C000)
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#define MEMU_BASE_ADDR (AIPS1_BASE_ADDR + 0X000060000)
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#define STCU_BASE_ADDR (AIPS1_BASE_ADDR + 0X000064000)
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#define SLFTST_CTRL_BASE_ADDR (AIPS1_BASE_ADDR + 0X000066000)
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#define MCT_BASE_ADDR (AIPS1_BASE_ADDR + 0X000068000)
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#define REP_BASE_ADDR (AIPS1_BASE_ADDR + 0X00006A000)
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#define MBIST_CONTROLLER_BASE_ADDR (AIPS1_BASE_ADDR + 0X00006C000)
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#define BOOT_LOADER_BASE_ADDR (AIPS1_BASE_ADDR + 0X00006F000)
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/* TODO Remove this after the IOMUX framework is implemented */
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#define IOMUXC_BASE_ADDR SIUL2_BASE_ADDR
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/* MUX mode and PAD ctrl are in one register */
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#define CONFIG_IOMUX_SHARE_CONF_REG
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#define FEC_QUIRK_ENET_MAC
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#define I2C_QUIRK_REG
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/* MSCM interrupt router */
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#define MSCM_IRSPRC_CPn_EN 3
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#define MSCM_IRSPRC_NUM 176
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#define MSCM_CPXTYPE_RYPZ_MASK 0xFF
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#define MSCM_CPXTYPE_RYPZ_OFFSET 0
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#define MSCM_CPXTYPE_PERS_MASK 0xFFFFFF00
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#define MSCM_CPXTYPE_PERS_OFFSET 8
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#define MSCM_CPXTYPE_PERS_A53 0x413533
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#define MSCM_CPXTYPE_PERS_CM4 0x434d34
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#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
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#include <asm/types.h>
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/* System Reset Controller (SRC) */
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struct src {
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u32 bmr1;
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u32 bmr2;
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u32 gpr1_boot;
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u32 reserved_0x00C[61];
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u32 gpr1;
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u32 gpr2;
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u32 gpr3;
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u32 gpr4;
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u32 gpr5;
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u32 gpr6;
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u32 gpr7;
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u32 reserved_0x11C[1];
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u32 gpr9;
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u32 gpr10;
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u32 gpr11;
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u32 gpr12;
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u32 gpr13;
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u32 gpr14;
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u32 gpr15;
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u32 gpr16;
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u32 reserved_0x140[1];
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u32 gpr17;
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u32 gpr18;
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u32 gpr19;
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u32 gpr20;
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u32 gpr21;
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u32 gpr22;
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u32 gpr23;
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u32 gpr24;
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u32 gpr25;
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u32 gpr26;
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u32 gpr27;
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u32 reserved_0x16C[5];
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u32 pcie_config1;
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u32 ddr_self_ref_ctrl;
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u32 pcie_config0;
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u32 reserved_0x18C[4];
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u32 soc_misc_config2;
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};
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/* SRC registers definitions */
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/* SRC_GPR1 */
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#define SRC_GPR1_PLL_SOURCE(pll,val)( ((val) & SRC_GPR1_PLL_SOURCE_MASK) << \
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(SRC_GPR1_PLL_OFFSET + (pll)) )
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#define SRC_GPR1_PLL_SOURCE_MASK (0x1)
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#define SRC_GPR1_PLL_OFFSET (27)
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#define SRC_GPR1_FIRC_CLK_SOURCE (0x0)
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#define SRC_GPR1_XOSC_CLK_SOURCE (0x1)
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/* Periodic Interrupt Timer (PIT) */
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struct pit_reg {
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u32 mcr;
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u32 recv0[55];
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u32 ltmr64h;
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u32 ltmr64l;
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u32 recv1[6];
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u32 ldval0;
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u32 cval0;
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u32 tctrl0;
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u32 tflg0;
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u32 ldval1;
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u32 cval1;
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u32 tctrl1;
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u32 tflg1;
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u32 ldval2;
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u32 cval2;
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u32 tctrl2;
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u32 tflg2;
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u32 ldval3;
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u32 cval3;
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u32 tctrl3;
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u32 tflg3;
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u32 ldval4;
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u32 cval4;
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u32 tctrl4;
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u32 tflg4;
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u32 ldval5;
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u32 cval5;
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u32 tctrl5;
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u32 tflg5;
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};
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/* Watchdog Timer (WDOG) */
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struct wdog_regs {
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u32 cr;
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u32 ir;
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u32 to;
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u32 wn;
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u32 sr;
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u32 co;
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u32 sk;
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};
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/* UART */
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struct linflex_fsl {
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u32 lincr1;
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u32 linier;
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u32 linsr;
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u32 linesr;
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u32 uartcr;
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u32 uartsr;
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u32 lintcsr;
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u32 linocr;
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u32 lintocr;
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u32 linfbrr;
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u32 linibrr;
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u32 lincfr;
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u32 lincr2;
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u32 bidr;
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u32 bdrl;
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u32 bdrm;
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u32 ifer;
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u32 ifmi;
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u32 ifmr;
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u32 ifcr0;
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u32 ifcr1;
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u32 ifcr2;
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u32 ifcr3;
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u32 ifcr4;
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u32 ifcr5;
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u32 ifcr6;
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u32 ifcr7;
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u32 ifcr8;
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u32 ifcr9;
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u32 ifcr10;
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u32 ifcr11;
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u32 ifcr12;
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u32 ifcr13;
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u32 ifcr14;
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u32 ifcr15;
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u32 gcr;
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u32 uartpto;
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u32 uartcto;
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u32 dmatxe;
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u32 dmarxe;
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};
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/* MSCM Interrupt Router */
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struct mscm_ir {
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u32 cpxtype; /* Processor x Type Register */
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u32 cpxnum; /* Processor x Number Register */
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u32 cpxmaster; /* Processor x Master Number Register */
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u32 cpxcount; /* Processor x Count Register */
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u32 cpxcfg0; /* Processor x Configuration 0 Register */
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u32 cpxcfg1; /* Processor x Configuration 1 Register */
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u32 cpxcfg2; /* Processor x Configuration 2 Register */
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u32 cpxcfg3; /* Processor x Configuration 3 Register */
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u32 cp0type; /* Processor 0 Type Register */
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u32 cp0num; /* Processor 0 Number Register */
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u32 cp0master; /* Processor 0 Master Number Register */
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u32 cp0count; /* Processor 0 Count Register */
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u32 cp0cfg0; /* Processor 0 Configuration 0 Register */
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u32 cp0cfg1; /* Processor 0 Configuration 1 Register */
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u32 cp0cfg2; /* Processor 0 Configuration 2 Register */
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u32 cp0cfg3; /* Processor 0 Configuration 3 Register */
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u32 cp1type; /* Processor 1 Type Register */
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u32 cp1num; /* Processor 1 Number Register */
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u32 cp1master; /* Processor 1 Master Number Register */
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u32 cp1count; /* Processor 1 Count Register */
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u32 cp1cfg0; /* Processor 1 Configuration 0 Register */
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u32 cp1cfg1; /* Processor 1 Configuration 1 Register */
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u32 cp1cfg2; /* Processor 1 Configuration 2 Register */
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u32 cp1cfg3; /* Processor 1 Configuration 3 Register */
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u32 reserved_0x060[232];
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u32 ocmdr0; /* On-Chip Memory Descriptor Register */
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u32 reserved_0x404[2];
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u32 ocmdr3; /* On-Chip Memory Descriptor Register */
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u32 reserved_0x410[28];
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u32 tcmdr[4]; /* Generic Tightly Coupled Memory Descriptor Register */
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u32 reserved_0x490[28];
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u32 cpce0; /* Core Parity Checking Enable Register 0 */
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u32 reserved_0x504[191];
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u32 ircp0ir; /* Interrupt Router CP0 Interrupt Register */
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u32 ircp1ir; /* Interrupt Router CP1 Interrupt Register */
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u32 reserved_0x808[6];
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u32 ircpgir; /* Interrupt Router CPU Generate Interrupt Register */
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u32 reserved_0x824[23];
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u16 irsprc[176]; /* Interrupt Router Shared Peripheral Routing Control Register */
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u32 reserved_0x9e0[136];
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u32 iahbbe0; /* Gasket Burst Enable Register */
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u32 reserved_0xc04[63];
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u32 ipcge; /* Interconnect Parity Checking Global Enable Register */
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u32 reserved_0xd04[3];
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u32 ipce[4]; /* Interconnect Parity Checking Enable Register */
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u32 reserved_0xd20[8];
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u32 ipcgie; /* Interconnect Parity Checking Global Injection Enable Register */
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u32 reserved_0xd44[3];
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u32 ipcie[4]; /* Interconnect Parity Checking Injection Enable Register */
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};
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#endif /* __ASSEMBLY__ */
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#endif /* __ASM_ARCH_IMX_REGS_H__ */
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