mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-19 03:08:31 +00:00
83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
54 lines
1.4 KiB
C
54 lines
1.4 KiB
C
// SPDX-License-Identifier: GPL-2.0+
|
|
/*
|
|
* Copyright 2015 Broadcom Corporation.
|
|
*/
|
|
|
|
#include <config.h>
|
|
#include <common.h>
|
|
#include <asm/io.h>
|
|
#include <asm/arch/sysmap.h>
|
|
#include <asm/kona-common/clk.h>
|
|
|
|
#include "dwc2_udc_otg_priv.h"
|
|
#include "bcm_udc_otg.h"
|
|
|
|
void otg_phy_init(struct dwc2_udc *dev)
|
|
{
|
|
/* turn on the USB OTG clocks */
|
|
clk_usb_otg_enable((void *)HSOTG_BASE_ADDR);
|
|
|
|
/* set Phy to driving mode */
|
|
wfld_clear(HSOTG_CTRL_BASE_ADDR + HSOTG_CTRL_PHY_P1CTL_OFFSET,
|
|
HSOTG_CTRL_PHY_P1CTL_NON_DRIVING_MASK);
|
|
|
|
udelay(100);
|
|
|
|
/* clear Soft Disconnect */
|
|
wfld_clear(HSOTG_BASE_ADDR + HSOTG_DCTL_OFFSET,
|
|
HSOTG_DCTL_SFTDISCON_MASK);
|
|
|
|
/* invoke Reset (active low) */
|
|
wfld_clear(HSOTG_CTRL_BASE_ADDR + HSOTG_CTRL_PHY_P1CTL_OFFSET,
|
|
HSOTG_CTRL_PHY_P1CTL_SOFT_RESET_MASK);
|
|
|
|
/* Reset needs to be asserted for 2ms */
|
|
udelay(2000);
|
|
|
|
/* release Reset */
|
|
wfld_set(HSOTG_CTRL_BASE_ADDR + HSOTG_CTRL_PHY_P1CTL_OFFSET,
|
|
HSOTG_CTRL_PHY_P1CTL_SOFT_RESET_MASK,
|
|
HSOTG_CTRL_PHY_P1CTL_SOFT_RESET_MASK);
|
|
}
|
|
|
|
void otg_phy_off(struct dwc2_udc *dev)
|
|
{
|
|
/* Soft Disconnect */
|
|
wfld_set(HSOTG_BASE_ADDR + HSOTG_DCTL_OFFSET,
|
|
HSOTG_DCTL_SFTDISCON_MASK,
|
|
HSOTG_DCTL_SFTDISCON_MASK);
|
|
|
|
/* set Phy to non-driving (reset) mode */
|
|
wfld_set(HSOTG_CTRL_BASE_ADDR + HSOTG_CTRL_PHY_P1CTL_OFFSET,
|
|
HSOTG_CTRL_PHY_P1CTL_NON_DRIVING_MASK,
|
|
HSOTG_CTRL_PHY_P1CTL_NON_DRIVING_MASK);
|
|
}
|