mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-17 18:28:55 +00:00
583f1b2f10
There is currently a problem that U-Boot can not work on ARMv4
because assembly imlementations of memcpy() and some other functions
use "bx lr" instruction that is not available on ARMv4 ("mov pc, lr"
should be used instead).
A working preprocessor-based solution to this problem is found in
arch/arm/lib/relocate.S. Move it to the "ret" macro in
arch/arm/include/asm/assembler.h and change all "bx lr" code
to "ret lr" in functions that may run on ARMv4. Linux source code
deals with this problem in the same manner.
v1 -> v2:
Comment update. Pointed out by Andre Przywara.
Signed-off-by: Sergei Antonov <saproj@gmail.com>
CC: Samuel Holland <samuel@sholland.org>
CC: Ye Li <ye.li@nxp.com>
CC: Simon Glass <sjg@chromium.org>
CC: Andre Przywara <andre.przywara@arm.com>
CC: Marek Vasut <marex@denx.de>
CC: Sean Anderson <sean.anderson@seco.com>
CC: Tom Rini <trini@konsulko.com>
264 lines
5.2 KiB
ArmAsm
264 lines
5.2 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* linux/arch/arm/lib/memcpy.S
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*
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* Author: Nicolas Pitre
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* Created: Sep 28, 2005
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* Copyright: MontaVista Software, Inc.
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*/
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#include <linux/linkage.h>
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#include <asm/assembler.h>
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#define LDR1W_SHIFT 0
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#define STR1W_SHIFT 0
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.macro ldr1w ptr reg abort
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W(ldr) \reg, [\ptr], #4
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.endm
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.macro ldr4w ptr reg1 reg2 reg3 reg4 abort
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ldmia \ptr!, {\reg1, \reg2, \reg3, \reg4}
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.endm
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.macro ldr8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
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ldmia \ptr!, {\reg1, \reg2, \reg3, \reg4, \reg5, \reg6, \reg7, \reg8}
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.endm
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.macro ldr1b ptr reg cond=al abort
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ldrb\cond\() \reg, [\ptr], #1
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.endm
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.macro str1w ptr reg abort
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W(str) \reg, [\ptr], #4
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.endm
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.macro str8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
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stmia \ptr!, {\reg1, \reg2, \reg3, \reg4, \reg5, \reg6, \reg7, \reg8}
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.endm
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.macro str1b ptr reg cond=al abort
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strb\cond\() \reg, [\ptr], #1
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.endm
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.macro enter reg1 reg2
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stmdb sp!, {r0, \reg1, \reg2}
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.endm
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.macro exit reg1 reg2
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ldmfd sp!, {r0, \reg1, \reg2}
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.endm
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.text
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/* Prototype: void *memcpy(void *dest, const void *src, size_t n); */
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.syntax unified
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#if CONFIG_IS_ENABLED(SYS_THUMB_BUILD) && !defined(MEMCPY_NO_THUMB_BUILD)
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.thumb
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.thumb_func
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#endif
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ENTRY(memcpy)
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cmp r0, r1
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reteq lr
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enter r4, lr
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subs r2, r2, #4
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blt 8f
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ands ip, r0, #3
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PLD( pld [r1, #0] )
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bne 9f
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ands ip, r1, #3
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bne 10f
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1: subs r2, r2, #(28)
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stmfd sp!, {r5 - r8}
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blt 5f
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CALGN( ands ip, r0, #31 )
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CALGN( rsb r3, ip, #32 )
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CALGN( sbcsne r4, r3, r2 ) @ C is always set here
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CALGN( bcs 2f )
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CALGN( adr r4, 6f )
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CALGN( subs r2, r2, r3 ) @ C gets set
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CALGN( add pc, r4, ip )
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PLD( pld [r1, #0] )
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2: PLD( subs r2, r2, #96 )
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PLD( pld [r1, #28] )
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PLD( blt 4f )
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PLD( pld [r1, #60] )
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PLD( pld [r1, #92] )
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3: PLD( pld [r1, #124] )
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4: ldr8w r1, r3, r4, r5, r6, r7, r8, ip, lr, abort=20f
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subs r2, r2, #32
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str8w r0, r3, r4, r5, r6, r7, r8, ip, lr, abort=20f
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bge 3b
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PLD( cmn r2, #96 )
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PLD( bge 4b )
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5: ands ip, r2, #28
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rsb ip, ip, #32
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#if LDR1W_SHIFT > 0
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lsl ip, ip, #LDR1W_SHIFT
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#endif
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addne pc, pc, ip @ C is always clear here
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b 7f
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6:
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.rept (1 << LDR1W_SHIFT)
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W(nop)
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.endr
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ldr1w r1, r3, abort=20f
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ldr1w r1, r4, abort=20f
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ldr1w r1, r5, abort=20f
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ldr1w r1, r6, abort=20f
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ldr1w r1, r7, abort=20f
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ldr1w r1, r8, abort=20f
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ldr1w r1, lr, abort=20f
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#if LDR1W_SHIFT < STR1W_SHIFT
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lsl ip, ip, #STR1W_SHIFT - LDR1W_SHIFT
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#elif LDR1W_SHIFT > STR1W_SHIFT
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lsr ip, ip, #LDR1W_SHIFT - STR1W_SHIFT
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#endif
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add pc, pc, ip
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nop
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.rept (1 << STR1W_SHIFT)
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W(nop)
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.endr
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str1w r0, r3, abort=20f
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str1w r0, r4, abort=20f
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str1w r0, r5, abort=20f
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str1w r0, r6, abort=20f
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str1w r0, r7, abort=20f
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str1w r0, r8, abort=20f
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str1w r0, lr, abort=20f
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CALGN( bcs 2b )
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7: ldmfd sp!, {r5 - r8}
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8: movs r2, r2, lsl #31
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ldr1b r1, r3, ne, abort=21f
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ldr1b r1, r4, cs, abort=21f
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ldr1b r1, ip, cs, abort=21f
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str1b r0, r3, ne, abort=21f
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str1b r0, r4, cs, abort=21f
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str1b r0, ip, cs, abort=21f
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exit r4, lr
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ret lr
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9: rsb ip, ip, #4
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cmp ip, #2
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ldr1b r1, r3, gt, abort=21f
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ldr1b r1, r4, ge, abort=21f
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ldr1b r1, lr, abort=21f
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str1b r0, r3, gt, abort=21f
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str1b r0, r4, ge, abort=21f
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subs r2, r2, ip
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str1b r0, lr, abort=21f
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blt 8b
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ands ip, r1, #3
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beq 1b
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10: bic r1, r1, #3
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cmp ip, #2
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ldr1w r1, lr, abort=21f
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beq 17f
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bgt 18f
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.macro forward_copy_shift pull push
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subs r2, r2, #28
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blt 14f
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CALGN( ands ip, r0, #31 )
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CALGN( rsb ip, ip, #32 )
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CALGN( sbcsne r4, ip, r2 ) @ C is always set here
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CALGN( subcc r2, r2, ip )
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CALGN( bcc 15f )
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11: stmfd sp!, {r5 - r9}
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PLD( pld [r1, #0] )
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PLD( subs r2, r2, #96 )
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PLD( pld [r1, #28] )
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PLD( blt 13f )
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PLD( pld [r1, #60] )
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PLD( pld [r1, #92] )
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12: PLD( pld [r1, #124] )
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13: ldr4w r1, r4, r5, r6, r7, abort=19f
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mov r3, lr, lspull #\pull
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subs r2, r2, #32
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ldr4w r1, r8, r9, ip, lr, abort=19f
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orr r3, r3, r4, lspush #\push
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mov r4, r4, lspull #\pull
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orr r4, r4, r5, lspush #\push
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mov r5, r5, lspull #\pull
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orr r5, r5, r6, lspush #\push
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mov r6, r6, lspull #\pull
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orr r6, r6, r7, lspush #\push
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mov r7, r7, lspull #\pull
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orr r7, r7, r8, lspush #\push
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mov r8, r8, lspull #\pull
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orr r8, r8, r9, lspush #\push
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mov r9, r9, lspull #\pull
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orr r9, r9, ip, lspush #\push
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mov ip, ip, lspull #\pull
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orr ip, ip, lr, lspush #\push
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str8w r0, r3, r4, r5, r6, r7, r8, r9, ip, abort=19f
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bge 12b
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PLD( cmn r2, #96 )
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PLD( bge 13b )
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ldmfd sp!, {r5 - r9}
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14: ands ip, r2, #28
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beq 16f
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15: mov r3, lr, lspull #\pull
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ldr1w r1, lr, abort=21f
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subs ip, ip, #4
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orr r3, r3, lr, lspush #\push
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str1w r0, r3, abort=21f
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bgt 15b
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CALGN( cmp r2, #0 )
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CALGN( bge 11b )
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16: sub r1, r1, #(\push / 8)
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b 8b
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.endm
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forward_copy_shift pull=8 push=24
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17: forward_copy_shift pull=16 push=16
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18: forward_copy_shift pull=24 push=8
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/*
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* Abort preamble and completion macros.
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* If a fixup handler is required then those macros must surround it.
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* It is assumed that the fixup code will handle the private part of
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* the exit macro.
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*/
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.macro copy_abort_preamble
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19: ldmfd sp!, {r5 - r9}
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b 21f
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20: ldmfd sp!, {r5 - r8}
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21:
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.endm
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.macro copy_abort_end
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ldmfd sp!, {r4, lr}
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ret lr
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.endm
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ENDPROC(memcpy)
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