mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-09-23 08:01:59 +00:00
0ed384fd2f
The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_NOR namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
495 lines
17 KiB
C
495 lines
17 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright 2017, 2020-2021 NXP
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*/
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#ifndef __LS1088A_QDS_H
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#define __LS1088A_QDS_H
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#include "ls1088a_common.h"
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#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
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#define SYS_NO_FLASH
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#endif
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#define COUNTER_FREQUENCY_REAL (get_board_sys_clk()/4)
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#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
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#define SPD_EEPROM_ADDRESS 0x51
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/*
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* IFC Definitions
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*/
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#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
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#define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
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#define CFG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
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#define CFG_SYS_NOR_AMASK_EARLY IFC_AMASK(64*1024*1024)
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#define CONFIG_SYS_NOR0_CSPR \
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(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
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CSPR_PORT_SIZE_16 | \
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CSPR_MSEL_NOR | \
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CSPR_V)
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#define CONFIG_SYS_NOR0_CSPR_EARLY \
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(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \
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CSPR_PORT_SIZE_16 | \
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CSPR_MSEL_NOR | \
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CSPR_V)
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#define CONFIG_SYS_NOR1_CSPR \
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(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS) | \
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CSPR_PORT_SIZE_16 | \
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CSPR_MSEL_NOR | \
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CSPR_V)
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#define CONFIG_SYS_NOR1_CSPR_EARLY \
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(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS_EARLY) | \
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CSPR_PORT_SIZE_16 | \
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CSPR_MSEL_NOR | \
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CSPR_V)
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#define CFG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12)
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#define CFG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
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FTIM0_NOR_TEADC(0x5) | \
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FTIM0_NOR_TAVDS(0x6) | \
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FTIM0_NOR_TEAHC(0x5))
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#define CFG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
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FTIM1_NOR_TRAD_NOR(0x1a) | \
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FTIM1_NOR_TSEQRAD_NOR(0x13))
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#define CFG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x8) | \
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FTIM2_NOR_TCH(0x8) | \
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FTIM2_NOR_TWPH(0xe) | \
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FTIM2_NOR_TWP(0x1c))
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#define CFG_SYS_NOR_FTIM3 0x04000000
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#define CONFIG_SYS_IFC_CCR 0x01000000
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#ifndef SYS_NO_FLASH
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#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
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#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE,\
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CONFIG_SYS_FLASH_BASE + 0x40000000}
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#endif
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#endif
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#define CFG_SYS_NAND_CSPR_EXT (0x0)
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#define CFG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \
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| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
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| CSPR_MSEL_NAND /* MSEL = NAND */ \
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| CSPR_V)
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#define CFG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
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#define CFG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
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| CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
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| CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
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| CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
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| CSOR_NAND_PGS_2K /* Page Size = 2K */ \
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| CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
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| CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
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/* ONFI NAND Flash mode0 Timing Params */
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#define CFG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
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FTIM0_NAND_TWP(0x18) | \
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FTIM0_NAND_TWCHT(0x07) | \
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FTIM0_NAND_TWH(0x0a))
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#define CFG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
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FTIM1_NAND_TWBE(0x39) | \
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FTIM1_NAND_TRR(0x0e) | \
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FTIM1_NAND_TRP(0x18))
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#define CFG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
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FTIM2_NAND_TREH(0x0a) | \
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FTIM2_NAND_TWHRE(0x1e))
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#define CFG_SYS_NAND_FTIM3 0x0
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#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
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#define CONFIG_MTD_NAND_VERIFY_WRITE
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#define CONFIG_SYS_I2C_FPGA_ADDR 0x66
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#define QIXIS_LBMAP_SWITCH 6
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#define QIXIS_QMAP_MASK 0xe0
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#define QIXIS_QMAP_SHIFT 5
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#define QIXIS_LBMAP_MASK 0x0f
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#define QIXIS_LBMAP_SHIFT 0
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#define QIXIS_LBMAP_DFLTBANK 0x0e
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#define QIXIS_LBMAP_ALTBANK 0x2e
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#define QIXIS_LBMAP_SD 0x00
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#define QIXIS_LBMAP_EMMC 0x00
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#define QIXIS_LBMAP_IFC 0x00
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#define QIXIS_LBMAP_SD_QSPI 0x0e
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#define QIXIS_LBMAP_QSPI 0x0e
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#define QIXIS_RCW_SRC_IFC 0x25
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#define QIXIS_RCW_SRC_SD 0x40
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#define QIXIS_RCW_SRC_EMMC 0x41
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#define QIXIS_RCW_SRC_QSPI 0x62
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#define QIXIS_RST_CTL_RESET 0x41
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#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
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#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
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#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
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#define QIXIS_RST_FORCE_MEM 0x01
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#define QIXIS_STAT_PRES1 0xb
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#define QIXIS_SDID_MASK 0x07
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#define QIXIS_ESDHC_NO_ADAPTER 0x7
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#define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
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#define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
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| CSPR_PORT_SIZE_8 \
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| CSPR_MSEL_GPCM \
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| CSPR_V)
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#define SYS_FPGA_CSPR_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
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| CSPR_PORT_SIZE_8 \
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| CSPR_MSEL_GPCM \
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| CSPR_V)
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#define SYS_FPGA_AMASK IFC_AMASK(64 * 1024)
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#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
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#define CONFIG_SYS_FPGA_CSOR CSOR_GPCM_ADM_SHIFT(0)
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#else
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#define CONFIG_SYS_FPGA_CSOR CSOR_GPCM_ADM_SHIFT(12)
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#endif
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/* QIXIS Timing parameters*/
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#define SYS_FPGA_CS_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
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FTIM0_GPCM_TEADC(0x0e) | \
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FTIM0_GPCM_TEAHC(0x0e))
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#define SYS_FPGA_CS_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
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FTIM1_GPCM_TRAD(0x3f))
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#define SYS_FPGA_CS_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
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FTIM2_GPCM_TCH(0xf) | \
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FTIM2_GPCM_TWP(0x3E))
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#define SYS_FPGA_CS_FTIM3 0x0
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#ifdef CONFIG_TFABOOT
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#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
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#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY
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#define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR
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#define CONFIG_SYS_AMASK0 CFG_SYS_NOR_AMASK
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#define CONFIG_SYS_CSOR0 CFG_SYS_NOR_CSOR
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#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0
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#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1
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#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2
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#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3
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#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
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#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR_EARLY
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#define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR1_CSPR
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#define CONFIG_SYS_AMASK1 CFG_SYS_NOR_AMASK_EARLY
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#define CONFIG_SYS_AMASK1_FINAL CFG_SYS_NOR_AMASK
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#define CONFIG_SYS_CSOR1 CFG_SYS_NOR_CSOR
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#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0
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#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1
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#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2
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#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3
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#define CONFIG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT
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#define CONFIG_SYS_CSPR2 CFG_SYS_NAND_CSPR
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#define CONFIG_SYS_AMASK2 CFG_SYS_NAND_AMASK
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#define CONFIG_SYS_CSOR2 CFG_SYS_NAND_CSOR
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#define CONFIG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0
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#define CONFIG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1
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#define CONFIG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2
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#define CONFIG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3
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#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
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#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
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#define CONFIG_SYS_CSPR3_FINAL SYS_FPGA_CSPR_FINAL
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#define CONFIG_SYS_AMASK3 SYS_FPGA_AMASK
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#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
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#define CONFIG_SYS_CS3_FTIM0 SYS_FPGA_CS_FTIM0
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#define CONFIG_SYS_CS3_FTIM1 SYS_FPGA_CS_FTIM1
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#define CONFIG_SYS_CS3_FTIM2 SYS_FPGA_CS_FTIM2
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#define CONFIG_SYS_CS3_FTIM3 SYS_FPGA_CS_FTIM3
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#else
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#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
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#define CONFIG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT
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#define CONFIG_SYS_CSPR0 CFG_SYS_NAND_CSPR
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#define CONFIG_SYS_AMASK0 CFG_SYS_NAND_AMASK
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#define CONFIG_SYS_CSOR0 CFG_SYS_NAND_CSOR
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#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0
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#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1
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#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2
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#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3
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#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_FPGA_CSPR_EXT
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#define CONFIG_SYS_CSPR2 CONFIG_SYS_FPGA_CSPR
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#define CONFIG_SYS_CSPR2_FINAL SYS_FPGA_CSPR_FINAL
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#define CONFIG_SYS_AMASK2 SYS_FPGA_AMASK
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#define CONFIG_SYS_CSOR2 CONFIG_SYS_FPGA_CSOR
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#define CONFIG_SYS_CS2_FTIM0 SYS_FPGA_CS_FTIM0
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#define CONFIG_SYS_CS2_FTIM1 SYS_FPGA_CS_FTIM1
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#define CONFIG_SYS_CS2_FTIM2 SYS_FPGA_CS_FTIM2
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#define CONFIG_SYS_CS2_FTIM3 SYS_FPGA_CS_FTIM3
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#else
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#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
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#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY
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#define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR
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#define CONFIG_SYS_AMASK0 CFG_SYS_NOR_AMASK
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#define CONFIG_SYS_CSOR0 CFG_SYS_NOR_CSOR
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#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0
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#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1
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#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2
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#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3
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#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
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#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR_EARLY
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#define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR1_CSPR
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#define CONFIG_SYS_AMASK1 CFG_SYS_NOR_AMASK_EARLY
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#define CONFIG_SYS_AMASK1_FINAL CFG_SYS_NOR_AMASK
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#define CONFIG_SYS_CSOR1 CFG_SYS_NOR_CSOR
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#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0
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#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1
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#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2
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#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3
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#define CONFIG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT
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#define CONFIG_SYS_CSPR2 CFG_SYS_NAND_CSPR
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#define CONFIG_SYS_AMASK2 CFG_SYS_NAND_AMASK
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#define CONFIG_SYS_CSOR2 CFG_SYS_NAND_CSOR
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#define CONFIG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0
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#define CONFIG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1
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#define CONFIG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2
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#define CONFIG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3
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#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
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#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
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#define CONFIG_SYS_CSPR3_FINAL SYS_FPGA_CSPR_FINAL
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#define CONFIG_SYS_AMASK3 SYS_FPGA_AMASK
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#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
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#define CONFIG_SYS_CS3_FTIM0 SYS_FPGA_CS_FTIM0
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#define CONFIG_SYS_CS3_FTIM1 SYS_FPGA_CS_FTIM1
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#define CONFIG_SYS_CS3_FTIM2 SYS_FPGA_CS_FTIM2
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#define CONFIG_SYS_CS3_FTIM3 SYS_FPGA_CS_FTIM3
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#endif
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#endif
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#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
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/*
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* I2C bus multiplexer
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*/
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#define I2C_MUX_PCA_ADDR_PRI 0x77
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#define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */
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#define I2C_RETIMER_ADDR 0x18
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#define I2C_RETIMER_ADDR2 0x19
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#define I2C_MUX_CH_DEFAULT 0x8
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#define I2C_MUX_CH5 0xD
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#define I2C_MUX_CH_VOL_MONITOR 0xA
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/* Voltage monitor on channel 2*/
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#define I2C_VOL_MONITOR_ADDR 0x63
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#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
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#define I2C_VOL_MONITOR_BUS_V_OVF 0x1
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#define I2C_VOL_MONITOR_BUS_V_SHIFT 3
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#define I2C_SVDD_MONITOR_ADDR 0x4F
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/* The lowest and highest voltage allowed for LS1088AQDS */
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#define VDD_MV_MIN 819
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#define VDD_MV_MAX 1212
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#define PWM_CHANNEL0 0x0
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/*
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* RTC configuration
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*/
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#define RTC
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#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/
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#ifdef CONFIG_FSL_DSPI
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#if !defined(CONFIG_TFABOOT) && \
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!defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
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#endif
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#endif
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#define COMMON_ENV \
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"kernelheader_addr_r=0x80200000\0" \
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"fdtheader_addr_r=0x80100000\0" \
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"kernel_addr_r=0x81000000\0" \
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"fdt_addr_r=0x90000000\0" \
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"load_addr=0xa0000000\0"
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/* Initial environment variables */
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#ifdef CONFIG_NXP_ESBC
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#undef CONFIG_EXTRA_ENV_SETTINGS
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#define CONFIG_EXTRA_ENV_SETTINGS \
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COMMON_ENV \
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"hwconfig=fsl_ddr:bank_intlv=auto\0" \
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"loadaddr=0x90100000\0" \
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"kernel_addr=0x100000\0" \
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"ramdisk_addr=0x800000\0" \
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"ramdisk_size=0x2000000\0" \
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"fdt_high=0xa0000000\0" \
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"initrd_high=0xffffffffffffffff\0" \
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"kernel_start=0x1000000\0" \
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"kernel_load=0xa0000000\0" \
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"kernel_size=0x2800000\0" \
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"mcinitcmd=sf probe 0:0;sf read 0xa0a00000 0xa00000 0x200000;" \
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"sf read 0xa0640000 0x640000 0x4000; esbc_validate 0xa0640000;" \
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"sf read 0xa0e00000 0xe00000 0x100000;" \
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"sf read 0xa0680000 0x680000 0x4000;esbc_validate 0xa0680000;" \
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"fsl_mc start mc 0xa0a00000 0xa0e00000\0" \
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"mcmemsize=0x70000000 \0"
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#else /* if !(CONFIG_NXP_ESBC) */
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#ifdef CONFIG_TFABOOT
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#define QSPI_MC_INIT_CMD \
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"sf probe 0:0;sf read 0x80a00000 0xA00000 0x200000;" \
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"sf read 0x80e00000 0xE00000 0x100000;" \
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"fsl_mc start mc 0x80a00000 0x80e00000\0"
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#define SD_MC_INIT_CMD \
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"mmcinfo;mmc read 0x80a00000 0x5000 0x1000;" \
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"mmc read 0x80e00000 0x7000 0x800;" \
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"fsl_mc start mc 0x80a00000 0x80e00000\0"
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#define IFC_MC_INIT_CMD \
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"fsl_mc start mc 0x580A00000 0x580E00000\0"
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#undef CONFIG_EXTRA_ENV_SETTINGS
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#define CONFIG_EXTRA_ENV_SETTINGS \
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COMMON_ENV \
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"hwconfig=fsl_ddr:bank_intlv=auto\0" \
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"loadaddr=0x90100000\0" \
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"kernel_addr=0x100000\0" \
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"kernel_addr_sd=0x800\0" \
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"ramdisk_addr=0x800000\0" \
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"ramdisk_size=0x2000000\0" \
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"fdt_high=0xa0000000\0" \
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"initrd_high=0xffffffffffffffff\0" \
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"kernel_start=0x1000000\0" \
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"kernel_start_sd=0x8000\0" \
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"kernel_load=0xa0000000\0" \
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"kernel_size=0x2800000\0" \
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"kernel_size_sd=0x14000\0" \
|
|
"mcinitcmd=sf probe 0:0;sf read 0x80a00000 0xA00000 0x200000;" \
|
|
"sf read 0x80e00000 0xE00000 0x100000;" \
|
|
"fsl_mc start mc 0x80a00000 0x80e00000\0" \
|
|
"mcmemsize=0x70000000 \0" \
|
|
"BOARD=ls1088aqds\0" \
|
|
"scriptaddr=0x80000000\0" \
|
|
"scripthdraddr=0x80080000\0" \
|
|
BOOTENV \
|
|
"boot_scripts=ls1088aqds_boot.scr\0" \
|
|
"boot_script_hdr=hdr_ls1088aqds_bs.out\0" \
|
|
"scan_dev_for_boot_part=" \
|
|
"part list ${devtype} ${devnum} devplist; " \
|
|
"env exists devplist || setenv devplist 1; " \
|
|
"for distro_bootpart in ${devplist}; do " \
|
|
"if fstype ${devtype} " \
|
|
"${devnum}:${distro_bootpart} " \
|
|
"bootfstype; then " \
|
|
"run scan_dev_for_boot; " \
|
|
"fi; " \
|
|
"done\0" \
|
|
"boot_a_script=" \
|
|
"load ${devtype} ${devnum}:${distro_bootpart} " \
|
|
"${scriptaddr} ${prefix}${script}; " \
|
|
"env exists secureboot && load ${devtype} " \
|
|
"${devnum}:${distro_bootpart} " \
|
|
"${scripthdraddr} ${prefix}${boot_script_hdr}; "\
|
|
"env exists secureboot " \
|
|
"&& esbc_validate ${scripthdraddr};" \
|
|
"source ${scriptaddr}\0" \
|
|
"qspi_bootcmd=echo Trying load from qspi..; " \
|
|
"sf probe 0:0; " \
|
|
"sf read 0x80001000 0xd00000 0x100000; " \
|
|
"fsl_mc lazyapply dpl 0x80001000 && " \
|
|
"sf read $kernel_load $kernel_start " \
|
|
"$kernel_size && bootm $kernel_load#$BOARD\0" \
|
|
"sd_bootcmd=echo Trying load from sd card..; " \
|
|
"mmcinfo;mmc read 0x80001000 0x6800 0x800; "\
|
|
"fsl_mc lazyapply dpl 0x80001000 && " \
|
|
"mmc read $kernel_load $kernel_start_sd " \
|
|
"$kernel_size_sd && bootm $kernel_load#$BOARD\0" \
|
|
"nor_bootcmd=echo Trying load from nor..; " \
|
|
"fsl_mc lazyapply dpl 0x580d00000 && " \
|
|
"cp.b $kernel_start $kernel_load " \
|
|
"$kernel_size && bootm $kernel_load#$BOARD\0"
|
|
#else
|
|
#if defined(CONFIG_QSPI_BOOT)
|
|
#undef CONFIG_EXTRA_ENV_SETTINGS
|
|
#define CONFIG_EXTRA_ENV_SETTINGS \
|
|
COMMON_ENV \
|
|
"hwconfig=fsl_ddr:bank_intlv=auto\0" \
|
|
"loadaddr=0x90100000\0" \
|
|
"kernel_addr=0x100000\0" \
|
|
"ramdisk_addr=0x800000\0" \
|
|
"ramdisk_size=0x2000000\0" \
|
|
"fdt_high=0xa0000000\0" \
|
|
"initrd_high=0xffffffffffffffff\0" \
|
|
"kernel_start=0x1000000\0" \
|
|
"kernel_load=0xa0000000\0" \
|
|
"kernel_size=0x2800000\0" \
|
|
"mcinitcmd=sf probe 0:0;sf read 0x80a00000 0xA00000 0x200000;" \
|
|
"sf read 0x80e00000 0xE00000 0x100000;" \
|
|
"fsl_mc start mc 0x80a00000 0x80e00000\0" \
|
|
"mcmemsize=0x70000000 \0"
|
|
#elif defined(CONFIG_SD_BOOT)
|
|
#undef CONFIG_EXTRA_ENV_SETTINGS
|
|
#define CONFIG_EXTRA_ENV_SETTINGS \
|
|
COMMON_ENV \
|
|
"hwconfig=fsl_ddr:bank_intlv=auto\0" \
|
|
"loadaddr=0x90100000\0" \
|
|
"kernel_addr=0x800\0" \
|
|
"ramdisk_addr=0x800000\0" \
|
|
"ramdisk_size=0x2000000\0" \
|
|
"fdt_high=0xa0000000\0" \
|
|
"initrd_high=0xffffffffffffffff\0" \
|
|
"kernel_start=0x8000\0" \
|
|
"kernel_load=0xa0000000\0" \
|
|
"kernel_size=0x14000\0" \
|
|
"mcinitcmd=mmcinfo;mmc read 0x80a00000 0x5000 0x1000;" \
|
|
"mmc read 0x80e00000 0x7000 0x800;" \
|
|
"fsl_mc start mc 0x80a00000 0x80e00000\0" \
|
|
"mcmemsize=0x70000000 \0"
|
|
#else /* NOR BOOT */
|
|
#undef CONFIG_EXTRA_ENV_SETTINGS
|
|
#define CONFIG_EXTRA_ENV_SETTINGS \
|
|
COMMON_ENV \
|
|
"hwconfig=fsl_ddr:bank_intlv=auto\0" \
|
|
"loadaddr=0x90100000\0" \
|
|
"kernel_addr=0x100000\0" \
|
|
"ramdisk_addr=0x800000\0" \
|
|
"ramdisk_size=0x2000000\0" \
|
|
"fdt_high=0xa0000000\0" \
|
|
"initrd_high=0xffffffffffffffff\0" \
|
|
"kernel_start=0x1000000\0" \
|
|
"kernel_load=0xa0000000\0" \
|
|
"kernel_size=0x2800000\0" \
|
|
"mcinitcmd=fsl_mc start mc 0x580A00000 0x580E00000\0" \
|
|
"mcmemsize=0x70000000 \0"
|
|
#endif
|
|
#endif /* CONFIG_TFABOOT */
|
|
#endif /* CONFIG_NXP_ESBC */
|
|
|
|
#ifdef CONFIG_TFABOOT
|
|
#define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \
|
|
"env exists secureboot && esbc_halt;;"
|
|
#define IFC_NOR_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd; " \
|
|
"env exists secureboot && esbc_halt;;"
|
|
#define SD_BOOTCOMMAND "run distro_bootcmd; run sd_bootcmd; " \
|
|
"env exists secureboot && esbc_halt;;"
|
|
#endif
|
|
|
|
#ifdef CONFIG_FSL_MC_ENET
|
|
#define RGMII_PHY1_ADDR 0x1
|
|
#define RGMII_PHY2_ADDR 0x2
|
|
#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
|
|
#define SGMII_CARD_PORT2_PHY_ADDR 0x1d
|
|
#define SGMII_CARD_PORT3_PHY_ADDR 0x1E
|
|
#define SGMII_CARD_PORT4_PHY_ADDR 0x1F
|
|
|
|
#define XQSGMII_CARD_PHY1_PORT0_ADDR 0x0
|
|
#define XQSGMII_CARD_PHY1_PORT1_ADDR 0x1
|
|
#define XQSGMII_CARD_PHY1_PORT2_ADDR 0x2
|
|
#define XQSGMII_CARD_PHY1_PORT3_ADDR 0x3
|
|
#define XQSGMII_CARD_PHY2_PORT0_ADDR 0x4
|
|
#define XQSGMII_CARD_PHY2_PORT1_ADDR 0x5
|
|
#define XQSGMII_CARD_PHY2_PORT2_ADDR 0x6
|
|
#define XQSGMII_CARD_PHY2_PORT3_ADDR 0x7
|
|
#define XQSGMII_CARD_PHY3_PORT0_ADDR 0x8
|
|
#define XQSGMII_CARD_PHY3_PORT1_ADDR 0x9
|
|
#define XQSGMII_CARD_PHY3_PORT2_ADDR 0xa
|
|
#define XQSGMII_CARD_PHY3_PORT3_ADDR 0xb
|
|
#define XQSGMII_CARD_PHY4_PORT0_ADDR 0xc
|
|
#define XQSGMII_CARD_PHY4_PORT1_ADDR 0xd
|
|
#define XQSGMII_CARD_PHY4_PORT2_ADDR 0xe
|
|
#define XQSGMII_CARD_PHY4_PORT3_ADDR 0xf
|
|
|
|
#endif
|
|
|
|
#define BOOT_TARGET_DEVICES(func) \
|
|
func(USB, usb, 0) \
|
|
func(MMC, mmc, 0) \
|
|
func(SCSI, scsi, 0) \
|
|
func(DHCP, dhcp, na)
|
|
#include <config_distro_bootcmd.h>
|
|
|
|
#include <asm/fsl_secure_boot.h>
|
|
|
|
#endif /* __LS1088A_QDS_H */
|