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https://github.com/AsahiLinux/u-boot
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91092132ba
The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_NS16550 namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
113 lines
2.5 KiB
C
113 lines
2.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright 2016 Freescale Semiconductor, Inc.
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* Copyright 2019 NXP
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR
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#define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE
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/*
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* DDR: 800 MHz ( 1600 MT/s data rate )
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*/
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#define DDR_SDRAM_CFG 0x470c0008
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#define DDR_CS0_BNDS 0x008000bf
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#define DDR_CS0_CONFIG 0x80014302
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#define DDR_TIMING_CFG_0 0x50550004
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#define DDR_TIMING_CFG_1 0xbcb38c56
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#define DDR_TIMING_CFG_2 0x0040d120
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#define DDR_TIMING_CFG_3 0x010e1000
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#define DDR_TIMING_CFG_4 0x00000001
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#define DDR_TIMING_CFG_5 0x03401400
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#define DDR_SDRAM_CFG_2 0x00401010
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#define DDR_SDRAM_MODE 0x00061c60
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#define DDR_SDRAM_MODE_2 0x00180000
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#define DDR_SDRAM_INTERVAL 0x18600618
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#define DDR_DDR_WRLVL_CNTL 0x8655f605
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#define DDR_DDR_WRLVL_CNTL_2 0x05060607
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#define DDR_DDR_WRLVL_CNTL_3 0x05050505
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#define DDR_DDR_CDR1 0x80040000
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#define DDR_DDR_CDR2 0x00000001
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#define DDR_SDRAM_CLK_CNTL 0x02000000
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#define DDR_DDR_ZQ_CNTL 0x89080600
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#define DDR_CS0_CONFIG_2 0
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#define DDR_SDRAM_CFG_MEM_EN 0x80000000
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#define SDRAM_CFG2_D_INIT 0x00000010
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#define DDR_CDR2_VREF_TRAIN_EN 0x00000080
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#define SDRAM_CFG2_FRC_SR 0x80000000
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#define SDRAM_CFG_BI 0x00000001
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#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
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#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
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/*
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* Serial Port
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*/
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#define CFG_SYS_NS16550_CLK get_serial_clock()
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/*
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* I2C
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*/
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/*
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* MMC
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*/
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/* SATA */
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#ifndef PCI_DEVICE_ID_FREESCALE_AHCI
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#define PCI_DEVICE_ID_FREESCALE_AHCI 0x0440
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#endif
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#define CONFIG_SCSI_DEV_LIST {PCI_VENDOR_ID_FREESCALE, \
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PCI_DEVICE_ID_FREESCALE_AHCI}
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/* SPI */
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/*
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* eTSEC
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*/
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#ifdef CONFIG_TSEC_ENET
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#define CONFIG_MII_DEFAULT_TSEC 1
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#define CONFIG_TSEC1 1
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#define CONFIG_TSEC1_NAME "eTSEC1"
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#define CONFIG_TSEC2 1
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#define CONFIG_TSEC2_NAME "eTSEC2"
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#define TSEC1_PHY_ADDR 1
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#define TSEC2_PHY_ADDR 3
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#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
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#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
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#define TSEC1_PHYIDX 0
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#define TSEC2_PHYIDX 0
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#endif
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#define FSL_PCIE_COMPAT "fsl,ls1021a-pcie"
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#define CONFIG_PEN_ADDR_BIG_ENDIAN
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#define CONFIG_SMP_PEN_ADDR 0x01ee0200
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#define CONFIG_HWCONFIG
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#define HWCONFIG_BUFFER_SIZE 256
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#define CONFIG_FSL_DEVICE_DISABLE
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
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"initrd_high=0xffffffff\0"
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/*
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* Miscellaneous configurable options
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*/
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#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
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#define CONFIG_LS102XA_STREAM_ID
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#include <asm/fsl_secure_boot.h>
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#endif
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