mirror of
https://github.com/AsahiLinux/u-boot
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91092132ba
The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_NS16550 namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
464 lines
15 KiB
C
464 lines
15 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright 2014 Freescale Semiconductor, Inc.
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* Copyright 2020-2021 NXP
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*/
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/*
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* T2080 RDB/PCIe board configuration file
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*/
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#ifndef __T2080RDB_H
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#define __T2080RDB_H
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#include <linux/stringify.h>
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#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
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/* High Level Configuration Options */
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#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
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#ifdef CONFIG_RAMBOOT_PBL
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#define RESET_VECTOR_OFFSET 0x27FFC
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#define BOOT_PAGE_OFFSET 0x27000
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#ifdef CONFIG_MTD_RAW_NAND
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#define CFG_SYS_NAND_U_BOOT_SIZE (768 << 10)
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#define CFG_SYS_NAND_U_BOOT_DST 0x00200000
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#define CFG_SYS_NAND_U_BOOT_START 0x00200000
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#endif
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#ifdef CONFIG_SPIFLASH
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#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
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#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
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#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000)
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#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000)
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#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10)
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#endif
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#ifdef CONFIG_SDCARD
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#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
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#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
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#define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000)
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#define CONFIG_SYS_MMC_U_BOOT_START (0x00200000)
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#define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
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#endif
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#endif /* CONFIG_RAMBOOT_PBL */
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#define CONFIG_SRIO_PCIE_BOOT_MASTER
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#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
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/* Set 1M boot space */
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#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_TEXT_BASE & 0xfff00000)
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#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
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(0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
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#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
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#endif
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#ifndef CONFIG_RESET_VECTOR_ADDRESS
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#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
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#endif
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/*
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* These can be toggled for performance analysis, otherwise use default.
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*/
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#ifdef CONFIG_DDR_ECC
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#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
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#endif
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/*
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* Config the L3 Cache as L3 SRAM
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*/
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#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
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#define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
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#define CONFIG_SYS_DCSRBAR 0xf0000000
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#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
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/*
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* DDR Setup
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*/
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#define CONFIG_VERY_BIG_RAM
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#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
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#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
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#define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */
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#define SPD_EEPROM_ADDRESS1 0x51
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#define SPD_EEPROM_ADDRESS2 0x52
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#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
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#define CTRL_INTLV_PREFERED cacheline
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/*
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* IFC Definitions
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*/
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#define CONFIG_SYS_FLASH_BASE 0xe8000000
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#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
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#define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
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#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
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CSPR_PORT_SIZE_16 | \
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CSPR_MSEL_NOR | \
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CSPR_V)
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#define CFG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
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/* NOR Flash Timing Params */
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#define CFG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
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#define CFG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
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FTIM0_NOR_TEADC(0x5) | \
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FTIM0_NOR_TEAHC(0x5))
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#define CFG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
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FTIM1_NOR_TRAD_NOR(0x1A) |\
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FTIM1_NOR_TSEQRAD_NOR(0x13))
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#define CFG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
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FTIM2_NOR_TCH(0x4) | \
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FTIM2_NOR_TWPH(0x0E) | \
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FTIM2_NOR_TWP(0x1c))
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#define CFG_SYS_NOR_FTIM3 0x0
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#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
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#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS }
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/* CPLD on IFC */
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#define CONFIG_SYS_CPLD_BASE 0xffdf0000
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#define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
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#define CONFIG_SYS_CSPR2_EXT (0xf)
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#define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \
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| CSPR_PORT_SIZE_8 \
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| CSPR_MSEL_GPCM \
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| CSPR_V)
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#define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024)
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#define CONFIG_SYS_CSOR2 0x0
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/* CPLD Timing parameters for IFC CS2 */
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#define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
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FTIM0_GPCM_TEADC(0x0e) | \
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FTIM0_GPCM_TEAHC(0x0e))
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#define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
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FTIM1_GPCM_TRAD(0x1f))
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#define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
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FTIM2_GPCM_TCH(0x8) | \
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FTIM2_GPCM_TWP(0x1f))
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#define CONFIG_SYS_CS2_FTIM3 0x0
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/* NAND Flash on IFC */
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#define CFG_SYS_NAND_BASE 0xff800000
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#define CFG_SYS_NAND_BASE_PHYS (0xf00000000ull | CFG_SYS_NAND_BASE)
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#define CFG_SYS_NAND_CSPR_EXT (0xf)
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#define CFG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \
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| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
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| CSPR_MSEL_NAND /* MSEL = NAND */ \
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| CSPR_V)
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#define CFG_SYS_NAND_AMASK IFC_AMASK(64*1024)
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#define CFG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
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| CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
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| CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
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| CSOR_NAND_RAL_3 /* RAL = 2Byes */ \
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| CSOR_NAND_PGS_2K /* Page Size = 2K */\
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| CSOR_NAND_SPRZ_64 /* Spare size = 64 */\
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| CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
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/* ONFI NAND Flash mode0 Timing Params */
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#define CFG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
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FTIM0_NAND_TWP(0x18) | \
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FTIM0_NAND_TWCHT(0x07) | \
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FTIM0_NAND_TWH(0x0a))
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#define CFG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
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FTIM1_NAND_TWBE(0x39) | \
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FTIM1_NAND_TRR(0x0e) | \
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FTIM1_NAND_TRP(0x18))
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#define CFG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
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FTIM2_NAND_TREH(0x0a) | \
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FTIM2_NAND_TWHRE(0x1e))
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#define CFG_SYS_NAND_FTIM3 0x0
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#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
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#if defined(CONFIG_MTD_RAW_NAND)
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#define CONFIG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT
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#define CONFIG_SYS_CSPR0 CFG_SYS_NAND_CSPR
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#define CONFIG_SYS_AMASK0 CFG_SYS_NAND_AMASK
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#define CONFIG_SYS_CSOR0 CFG_SYS_NAND_CSOR
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#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0
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#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1
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#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2
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#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3
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#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
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#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
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#define CONFIG_SYS_AMASK1 CFG_SYS_NOR_AMASK
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#define CONFIG_SYS_CSOR1 CFG_SYS_NOR_CSOR
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#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0
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#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1
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#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2
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#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3
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#else
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#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
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#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
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#define CONFIG_SYS_AMASK0 CFG_SYS_NOR_AMASK
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#define CONFIG_SYS_CSOR0 CFG_SYS_NOR_CSOR
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#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0
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#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1
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#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2
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#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3
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#define CONFIG_SYS_CSPR1_EXT CFG_SYS_NAND_CSPR_EXT
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#define CONFIG_SYS_CSPR1 CFG_SYS_NAND_CSPR
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#define CONFIG_SYS_AMASK1 CFG_SYS_NAND_AMASK
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#define CONFIG_SYS_CSOR1 CFG_SYS_NAND_CSOR
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#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NAND_FTIM0
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#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NAND_FTIM1
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#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NAND_FTIM2
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#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3
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#endif
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#define CONFIG_HWCONFIG
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/* define to use L1 as initial stack */
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#define CONFIG_L1_INIT_RAM
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#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
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#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
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#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
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/* The assembler doesn't like typecast */
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#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
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((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
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CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
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#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
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#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
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/*
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* Serial Port
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*/
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#define CFG_SYS_NS16550_CLK (get_bus_freq(0)/2)
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#define CONFIG_SYS_BAUDRATE_TABLE \
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{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
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#define CFG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
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#define CFG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
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#define CFG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
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#define CFG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
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/*
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* I2C
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*/
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#define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */
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#define I2C_MUX_PCA_ADDR_SEC1 0x75 /* I2C bus multiplexer,secondary 1 */
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#define I2C_MUX_PCA_ADDR_SEC2 0x76 /* I2C bus multiplexer,secondary 2 */
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#define I2C_MUX_CH_DEFAULT 0x8
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#define I2C_MUX_CH_VOL_MONITOR 0xa
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/* The lowest and highest voltage allowed for T208xRDB */
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#define VDD_MV_MIN 819
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#define VDD_MV_MAX 1212
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/*
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* RapidIO
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*/
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#define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
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#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
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#define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
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#define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
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#define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
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#define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
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/*
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* for slave u-boot IMAGE instored in master memory space,
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* PHYS must be aligned based on the SIZE
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*/
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#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
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#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
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#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
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#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
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/*
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* for slave UCODE and ENV instored in master memory space,
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* PHYS must be aligned based on the SIZE
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*/
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#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
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#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
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#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
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/* slave core release by master*/
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#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
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#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
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/*
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* SRIO_PCIE_BOOT - SLAVE
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*/
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#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
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#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
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#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
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(0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
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#endif
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/*
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* eSPI - Enhanced SPI
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*/
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/*
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* General PCI
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* Memory space is mapped 1-1, but I/O space must start from 0.
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*/
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/* controller 1, direct to uli, tgtid 3, Base address 20000 */
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#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
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#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
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#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
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#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
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/* controller 2, Slot 2, tgtid 2, Base address 201000 */
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#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
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#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
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#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
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#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
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/* controller 3, Slot 1, tgtid 1, Base address 202000 */
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#define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000
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#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc30000000ull
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#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
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#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
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/* controller 4, Base address 203000 */
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#define CONFIG_SYS_PCIE4_MEM_VIRT 0xc0000000
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#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc40000000ull
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#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
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/* Qman/Bman */
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#ifndef CONFIG_NOBQFMAN
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#define CONFIG_SYS_BMAN_NUM_PORTALS 18
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#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
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#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
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#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
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#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
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#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
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#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
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#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
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#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
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CONFIG_SYS_BMAN_CENA_SIZE)
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#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
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#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
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#define CONFIG_SYS_QMAN_NUM_PORTALS 18
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#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
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#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
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#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
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#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
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#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
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#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
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#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
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#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
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CONFIG_SYS_QMAN_CENA_SIZE)
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#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
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#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
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#define CONFIG_SYS_DPAA_FMAN
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#define CONFIG_SYS_DPAA_PME
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#define CONFIG_SYS_PMAN
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#define CONFIG_SYS_DPAA_DCE
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#define CONFIG_SYS_DPAA_RMAN /* RMan */
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#endif /* CONFIG_NOBQFMAN */
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#ifdef CONFIG_SYS_DPAA_FMAN
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#define RGMII_PHY1_ADDR 0x01 /* RealTek RTL8211E */
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#define RGMII_PHY2_ADDR 0x02
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#define CORTINA_PHY_ADDR1 0x0c /* Cortina CS4315 */
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#define CORTINA_PHY_ADDR2 0x0d
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/* Aquantia AQ1202 10G Base-T used by board revisions up to C */
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#define FM1_10GEC3_PHY_ADDR 0x00
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#define FM1_10GEC4_PHY_ADDR 0x01
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/* Aquantia AQR113C 10G Base-T used by board revisions D and up */
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#define AQR113C_PHY_ADDR1 0x00
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#define AQR113C_PHY_ADDR2 0x08
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#endif
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/*
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* USB
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*/
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|
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/*
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* SDHC
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*/
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#ifdef CONFIG_MMC
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#define CFG_SYS_FSL_ESDHC_ADDR CFG_SYS_MPC85xx_ESDHC_ADDR
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#endif
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/*
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* Dynamic MTD Partition support with mtdparts
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*/
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/*
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* Environment
|
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*/
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|
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/*
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* Miscellaneous configurable options
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|
*/
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|
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 64 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization.
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|
*/
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#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
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|
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/*
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|
* Environment Configuration
|
|
*/
|
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#define CONFIG_ROOTPATH "/opt/nfsroot"
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#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */
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|
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#define __USB_PHY_TYPE utmi
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|
|
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"hwconfig=fsl_ddr:" \
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"ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \
|
|
"bank_intlv=auto;" \
|
|
"usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
|
|
"netdev=eth0\0" \
|
|
"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
|
|
"ubootaddr=" __stringify(CONFIG_TEXT_BASE) "\0" \
|
|
"tftpflash=tftpboot $loadaddr $uboot && " \
|
|
"protect off $ubootaddr +$filesize && " \
|
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"erase $ubootaddr +$filesize && " \
|
|
"cp.b $loadaddr $ubootaddr $filesize && " \
|
|
"protect on $ubootaddr +$filesize && " \
|
|
"cmp.b $loadaddr $ubootaddr $filesize\0" \
|
|
"consoledev=ttyS0\0" \
|
|
"ramdiskaddr=2000000\0" \
|
|
"ramdiskfile=t2080rdb/ramdisk.uboot\0" \
|
|
"fdtaddr=1e00000\0" \
|
|
"fdtfile=t2080rdb/t2080rdb.dtb\0" \
|
|
"bdev=sda3\0"
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|
|
|
/*
|
|
* For emulation this causes u-boot to jump to the start of the
|
|
* proof point app code automatically
|
|
*/
|
|
#define PROOF_POINTS \
|
|
"setenv bootargs root=/dev/$bdev rw " \
|
|
"console=$consoledev,$baudrate $othbootargs;" \
|
|
"cpu 1 release 0x29000000 - - -;" \
|
|
"cpu 2 release 0x29000000 - - -;" \
|
|
"cpu 3 release 0x29000000 - - -;" \
|
|
"cpu 4 release 0x29000000 - - -;" \
|
|
"cpu 5 release 0x29000000 - - -;" \
|
|
"cpu 6 release 0x29000000 - - -;" \
|
|
"cpu 7 release 0x29000000 - - -;" \
|
|
"go 0x29000000"
|
|
|
|
#define HVBOOT \
|
|
"setenv bootargs config-addr=0x60000000; " \
|
|
"bootm 0x01000000 - 0x00f00000"
|
|
|
|
#define ALU \
|
|
"setenv bootargs root=/dev/$bdev rw " \
|
|
"console=$consoledev,$baudrate $othbootargs;" \
|
|
"cpu 1 release 0x01000000 - - -;" \
|
|
"cpu 2 release 0x01000000 - - -;" \
|
|
"cpu 3 release 0x01000000 - - -;" \
|
|
"cpu 4 release 0x01000000 - - -;" \
|
|
"cpu 5 release 0x01000000 - - -;" \
|
|
"cpu 6 release 0x01000000 - - -;" \
|
|
"cpu 7 release 0x01000000 - - -;" \
|
|
"go 0x01000000"
|
|
|
|
#include <asm/fsl_secure_boot.h>
|
|
|
|
#endif /* __T2080RDB_H */
|