mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-11 15:37:23 +00:00
9107ebe0d3
This is a compatibility step that allows both the older form
and the new form to co-exist for a while until the older can
be removed entirely.
All transformations are of the form:
Before:
#if (CONFIG_COMMANDS & CFG_CMD_AUTOSCRIPT)
After:
#if (CONFIG_COMMANDS & CFG_CMD_AUTOSCRIPT) || defined(CONFIG_CMD_AUTOSCRIPT)
Signed-off-by: Jon Loeliger <jdl@freescale.com>
94 lines
2.6 KiB
C
94 lines
2.6 KiB
C
/*
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* (C) Copyright 2007
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* Heiko Schocher, DENX Software Engineering, hs@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#if (CONFIG_COMMANDS & CFG_CMD_NAND) || defined(CONFIG_CMD_NAND)
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#include <nand.h>
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#include <asm/processor.h>
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#define readb(addr) *(volatile u_char *)(addr)
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#define readl(addr) *(volatile u_long *)(addr)
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#define writeb(d,addr) *(volatile u_char *)(addr) = (d)
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#define SC3_NAND_ALE 29 /* GPIO PIN 3 */
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#define SC3_NAND_CLE 30 /* GPIO PIN 2 */
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#define SC3_NAND_CE 27 /* GPIO PIN 5 */
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static void *sc3_io_base;
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static void *sc3_control_base = (void *)0xEF600700;
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static void sc3_nand_hwcontrol(struct mtd_info *mtd, int cmd)
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{
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switch (cmd) {
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case NAND_CTL_SETCLE:
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set_bit (SC3_NAND_CLE, sc3_control_base);
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break;
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case NAND_CTL_CLRCLE:
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clear_bit (SC3_NAND_CLE, sc3_control_base);
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break;
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case NAND_CTL_SETALE:
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set_bit (SC3_NAND_ALE, sc3_control_base);
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break;
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case NAND_CTL_CLRALE:
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clear_bit (SC3_NAND_ALE, sc3_control_base);
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break;
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case NAND_CTL_SETNCE:
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set_bit (SC3_NAND_CE, sc3_control_base);
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break;
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case NAND_CTL_CLRNCE:
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clear_bit (SC3_NAND_CE, sc3_control_base);
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break;
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}
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}
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static int sc3_nand_dev_ready(struct mtd_info *mtd)
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{
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if (!(readl(sc3_control_base + 0x1C) & 0x4000))
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return 0;
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return 1;
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}
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static void sc3_select_chip(struct mtd_info *mtd, int chip)
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{
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clear_bit (SC3_NAND_CE, sc3_control_base);
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}
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int board_nand_init(struct nand_chip *nand)
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{
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nand->eccmode = NAND_ECC_SOFT;
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sc3_io_base = (void *) CFG_NAND_BASE;
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/* Set address of NAND IO lines (Using Linear Data Access Region) */
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nand->IO_ADDR_R = (void __iomem *) sc3_io_base;
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nand->IO_ADDR_W = (void __iomem *) sc3_io_base;
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/* Reference hardware control function */
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nand->hwcontrol = sc3_nand_hwcontrol;
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nand->dev_ready = sc3_nand_dev_ready;
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nand->select_chip = sc3_select_chip;
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return 0;
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}
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#endif
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