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https://github.com/AsahiLinux/u-boot
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d96c26040e
These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
260 lines
6 KiB
C
260 lines
6 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2015 Freescale Semiconductor, Inc.
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* Copyright 2019 NXP.
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*/
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#include <common.h>
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#include <clock_legacy.h>
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#include <cpu_func.h>
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#include <linux/compiler.h>
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#include <asm/io.h>
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#include <asm/processor.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/soc.h>
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#include <fsl_ifc.h>
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#include "cpu.h"
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DECLARE_GLOBAL_DATA_PTR;
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#ifndef CONFIG_SYS_FSL_NUM_CC_PLLS
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#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
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#endif
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void get_sys_info(struct sys_info *sys_info)
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{
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struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
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/* rcw_tmp is needed to get FMAN clock, or to get cluster group A
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* mux 2 clock for LS1043A/LS1046A.
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*/
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#if defined(CONFIG_SYS_DPAA_FMAN) || \
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defined(CONFIG_TARGET_LS1046ARDB) || \
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defined(CONFIG_TARGET_LS1043ARDB)
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u32 rcw_tmp;
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#endif
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struct ccsr_clk *clk = (void *)(CONFIG_SYS_FSL_CLK_ADDR);
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unsigned int cpu;
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const u8 core_cplx_pll[8] = {
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[0] = 0, /* CC1 PPL / 1 */
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[1] = 0, /* CC1 PPL / 2 */
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[4] = 1, /* CC2 PPL / 1 */
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[5] = 1, /* CC2 PPL / 2 */
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};
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const u8 core_cplx_pll_div[8] = {
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[0] = 1, /* CC1 PPL / 1 */
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[1] = 2, /* CC1 PPL / 2 */
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[4] = 1, /* CC2 PPL / 1 */
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[5] = 2, /* CC2 PPL / 2 */
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};
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uint i, cluster;
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uint freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS];
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uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS];
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unsigned long sysclk = CONFIG_SYS_CLK_FREQ;
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unsigned long cluster_clk;
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sys_info->freq_systembus = sysclk;
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#ifndef CONFIG_CLUSTER_CLK_FREQ
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#define CONFIG_CLUSTER_CLK_FREQ CONFIG_SYS_CLK_FREQ
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#endif
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cluster_clk = CONFIG_CLUSTER_CLK_FREQ;
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#ifdef CONFIG_DDR_CLK_FREQ
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sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ;
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#else
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sys_info->freq_ddrbus = sysclk;
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#endif
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/* The freq_systembus is used to record frequency of platform PLL */
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sys_info->freq_systembus *= (gur_in32(&gur->rcwsr[0]) >>
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FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT) &
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FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK;
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#ifdef CONFIG_ARCH_LS1012A
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sys_info->freq_ddrbus = 2 * sys_info->freq_systembus;
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#else
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sys_info->freq_ddrbus *= (gur_in32(&gur->rcwsr[0]) >>
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FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_SHIFT) &
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FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_MASK;
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#endif
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for (i = 0; i < CONFIG_SYS_FSL_NUM_CC_PLLS; i++) {
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ratio[i] = (in_be32(&clk->pllcgsr[i].pllcngsr) >> 1) & 0xff;
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if (ratio[i] > 4)
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freq_c_pll[i] = cluster_clk * ratio[i];
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else
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freq_c_pll[i] = sys_info->freq_systembus * ratio[i];
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}
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for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) {
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cluster = fsl_qoriq_core_to_cluster(cpu);
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u32 c_pll_sel = (in_be32(&clk->clkcsr[cluster].clkcncsr) >> 27)
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& 0xf;
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u32 cplx_pll = core_cplx_pll[c_pll_sel];
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sys_info->freq_processor[cpu] =
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freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
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}
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#define HWA_CGA_M1_CLK_SEL 0xe0000000
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#define HWA_CGA_M1_CLK_SHIFT 29
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#ifdef CONFIG_SYS_DPAA_FMAN
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rcw_tmp = in_be32(&gur->rcwsr[7]);
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switch ((rcw_tmp & HWA_CGA_M1_CLK_SEL) >> HWA_CGA_M1_CLK_SHIFT) {
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case 2:
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sys_info->freq_fman[0] = freq_c_pll[0] / 2;
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break;
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case 3:
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sys_info->freq_fman[0] = freq_c_pll[0] / 3;
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break;
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case 4:
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sys_info->freq_fman[0] = freq_c_pll[0] / 4;
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break;
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case 5:
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sys_info->freq_fman[0] = sys_info->freq_systembus;
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break;
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case 6:
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sys_info->freq_fman[0] = freq_c_pll[1] / 2;
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break;
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case 7:
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sys_info->freq_fman[0] = freq_c_pll[1] / 3;
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break;
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default:
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printf("Error: Unknown FMan1 clock select!\n");
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break;
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}
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#endif
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#define HWA_CGA_M2_CLK_SEL 0x00000007
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#define HWA_CGA_M2_CLK_SHIFT 0
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#if defined(CONFIG_TARGET_LS1046ARDB) || defined(CONFIG_TARGET_LS1043ARDB)
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rcw_tmp = in_be32(&gur->rcwsr[15]);
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switch ((rcw_tmp & HWA_CGA_M2_CLK_SEL) >> HWA_CGA_M2_CLK_SHIFT) {
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case 1:
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sys_info->freq_cga_m2 = freq_c_pll[1];
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break;
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#if defined(CONFIG_TARGET_LS1046ARDB)
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case 2:
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sys_info->freq_cga_m2 = freq_c_pll[1] / 2;
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break;
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#endif
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case 3:
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sys_info->freq_cga_m2 = freq_c_pll[1] / 3;
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break;
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#if defined(CONFIG_TARGET_LS1046ARDB)
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case 6:
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sys_info->freq_cga_m2 = freq_c_pll[0] / 2;
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break;
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#endif
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default:
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printf("Error: Unknown cluster group A mux 2 clock select!\n");
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break;
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}
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#endif
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#if defined(CONFIG_FSL_IFC)
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sys_info->freq_localbus = sys_info->freq_systembus /
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CONFIG_SYS_FSL_IFC_CLK_DIV;
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#endif
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#ifdef CONFIG_SYS_DPAA_QBMAN
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sys_info->freq_qman = (sys_info->freq_systembus /
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CONFIG_SYS_FSL_PCLK_DIV) /
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CONFIG_SYS_FSL_QMAN_CLK_DIV;
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#endif
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}
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#ifdef CONFIG_SYS_DPAA_QBMAN
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unsigned long get_qman_freq(void)
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{
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struct sys_info sys_info;
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get_sys_info(&sys_info);
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return sys_info.freq_qman;
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}
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#endif
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int get_clocks(void)
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{
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struct sys_info sys_info;
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#ifdef CONFIG_FSL_ESDHC
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u32 clock = 0;
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#endif
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get_sys_info(&sys_info);
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gd->cpu_clk = sys_info.freq_processor[0];
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gd->bus_clk = sys_info.freq_systembus / CONFIG_SYS_FSL_PCLK_DIV;
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gd->mem_clk = sys_info.freq_ddrbus;
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#ifdef CONFIG_FSL_ESDHC
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#if defined(CONFIG_ARCH_LS1012A)
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clock = sys_info.freq_systembus;
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#elif defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
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clock = sys_info.freq_cga_m2;
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#endif
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gd->arch.sdhc_per_clk = clock / CONFIG_SYS_FSL_SDHC_CLK_DIV;
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gd->arch.sdhc_clk = gd->bus_clk / CONFIG_SYS_FSL_SDHC_CLK_DIV;
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#endif
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if (gd->cpu_clk != 0)
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return 0;
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else
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return 1;
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}
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/********************************************
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* get_bus_freq
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* return platform clock in Hz
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*********************************************/
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ulong get_bus_freq(ulong dummy)
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{
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if (!gd->bus_clk)
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get_clocks();
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return gd->bus_clk;
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}
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ulong get_ddr_freq(ulong dummy)
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{
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if (!gd->mem_clk)
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get_clocks();
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return gd->mem_clk;
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}
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int get_serial_clock(void)
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{
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return get_bus_freq(0) / CONFIG_SYS_FSL_DUART_CLK_DIV;
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}
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int get_i2c_freq(ulong dummy)
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{
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return get_bus_freq(0) / CONFIG_SYS_FSL_I2C_CLK_DIV;
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}
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int get_dspi_freq(ulong dummy)
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{
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return get_bus_freq(0) / CONFIG_SYS_FSL_DSPI_CLK_DIV;
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}
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#ifdef CONFIG_FSL_LPUART
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int get_uart_freq(ulong dummy)
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{
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return get_bus_freq(0) / CONFIG_SYS_FSL_LPUART_CLK_DIV;
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}
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#endif
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unsigned int mxc_get_clock(enum mxc_clock clk)
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{
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switch (clk) {
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case MXC_I2C_CLK:
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return get_i2c_freq(0);
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case MXC_DSPI_CLK:
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return get_dspi_freq(0);
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#ifdef CONFIG_FSL_LPUART
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case MXC_UART_CLK:
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return get_uart_freq(0);
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#endif
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default:
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printf("Unsupported clock\n");
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}
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return 0;
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}
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