mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-11 05:42:58 +00:00
6d82517836
Now that new SPI NOR layer uses stateless 4 byte opcodes by default, don't enable SPI_FLASH_BAR. For SPI controllers that cannot support 4-byte addressing, (stm32_qspi.c, fsl_qspi.c, mtk_qspi.c, ich.c, renesas_rpc_spi.c) add an imply clause to enable SPI_FLASH_BAR so as to not break functionality. Signed-off-by: Vignesh R <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Tested-by: Stefan Roese <sr@denx.de> Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
66 lines
1.7 KiB
Text
66 lines
1.7 KiB
Text
CONFIG_ARM=y
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CONFIG_ARCH_SOCFPGA=y
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CONFIG_SYS_TEXT_BASE=0x01000040
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CONFIG_SYS_MALLOC_F_LEN=0x2000
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CONFIG_TARGET_SOCFPGA_SR1500=y
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CONFIG_SPL=y
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CONFIG_SPL_STACK_R_ADDR=0x00800000
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CONFIG_DISTRO_DEFAULTS=y
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CONFIG_NR_DRAM_BANKS=1
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CONFIG_FIT=y
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# CONFIG_USE_BOOTCOMMAND is not set
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CONFIG_SYS_CONSOLE_IS_IN_ENV=y
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CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
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CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y
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CONFIG_SYS_CONSOLE_INFO_QUIET=y
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CONFIG_DEFAULT_FDT_FILE="socfpga_cyclone5_sr1500.dtb"
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CONFIG_VERSION_VARIABLE=y
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# CONFIG_DISPLAY_BOARDINFO is not set
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CONFIG_DISPLAY_BOARDINFO_LATE=y
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CONFIG_BOARD_EARLY_INIT_F=y
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CONFIG_SPL_SYS_MALLOC_SIMPLE=y
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CONFIG_SPL_STACK_R=y
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CONFIG_SPL_SPI_LOAD=y
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CONFIG_CMD_ASKENV=y
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CONFIG_CMD_GREPENV=y
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CONFIG_CMD_MEMTEST=y
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# CONFIG_CMD_FLASH is not set
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CONFIG_CMD_GPIO=y
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CONFIG_CMD_I2C=y
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CONFIG_CMD_MMC=y
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CONFIG_CMD_SF=y
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CONFIG_CMD_SPI=y
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CONFIG_CMD_CACHE=y
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CONFIG_CMD_TIME=y
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CONFIG_CMD_EXT4_WRITE=y
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CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0"
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CONFIG_MTDPARTS_DEFAULT="mtdparts=ff705000.spi.0:1m(u-boot),256k(env1),256k(env2),14848k(boot),16m(rootfs),-@1536k(UBI)0"
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CONFIG_CMD_UBI=y
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# CONFIG_ISO_PARTITION is not set
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# CONFIG_EFI_PARTITION is not set
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CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_sr1500"
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CONFIG_ENV_IS_IN_SPI_FLASH=y
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CONFIG_SPL_DM=y
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CONFIG_SPL_DM_SEQ_ALIAS=y
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CONFIG_BOOTCOUNT_LIMIT=y
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CONFIG_SYS_BOOTCOUNT_ADDR=0xfffffff8
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CONFIG_FPGA_SOCFPGA=y
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CONFIG_DM_GPIO=y
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CONFIG_DWAPB_GPIO=y
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CONFIG_DM_I2C=y
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CONFIG_SYS_I2C_DW=y
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CONFIG_DM_MMC=y
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CONFIG_MMC_DW=y
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CONFIG_MTD_DEVICE=y
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CONFIG_SPI_FLASH=y
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CONFIG_SPI_FLASH_STMICRO=y
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# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
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CONFIG_PHY_MARVELL=y
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CONFIG_DM_ETH=y
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CONFIG_PHY_GIGE=y
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CONFIG_ETH_DESIGNWARE=y
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CONFIG_MII=y
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CONFIG_DM_RESET=y
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CONFIG_SPI=y
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CONFIG_CADENCE_QSPI=y
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CONFIG_USE_TINY_PRINTF=y
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