mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-26 22:52:18 +00:00
90d7cc42b3
Due to incorrect placement of the clock gate cell in the ldb_di[x]_clk tree, the glitchy parent mux of ldb_di[x]_clk can cause a glitch to enter the ldb_di_ipu_div divider. If the divider gets locked up, no ldb_di[x]_clk is generated, and the LVDS display will hang when the ipu_di_clk is sourced from ldb_di_clk. To fix the problem, both the new and current parent of the ldb_di_clk should be disabled before the switch. This patch ensures that correct steps are followed when ldb_di_clk parent is switched in the beginning of boot. This patch was ported from the 3.10.17 NXP kernel http://git.freescale.com/git/cgit.cgi/imx/linux-2.6-imx.git/commit/?h=imx_3.10.17_1.0.1_ga&id=eecbe9a52587cf9eec30132fb9b8a6761f3a1e6d NXP errata number: ERR009219, EB821 Signed-off-by: Akshay Bhat <akshay.bhat@timesys.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> |
||
|---|---|---|
| .. | ||
| clock.h | ||
| crm_regs.h | ||
| gpio.h | ||
| imx-rdc.h | ||
| imx-regs.h | ||
| iomux.h | ||
| mx6-ddr.h | ||
| mx6-pins.h | ||
| mx6dl-ddr.h | ||
| mx6dl_pins.h | ||
| mx6q-ddr.h | ||
| mx6q_pins.h | ||
| mx6sl-ddr.h | ||
| mx6sl_pins.h | ||
| mx6sx-ddr.h | ||
| mx6sx_pins.h | ||
| mx6sx_rdc.h | ||
| mx6ul-ddr.h | ||
| mx6ul_pins.h | ||
| mxc_hdmi.h | ||
| sys_proto.h | ||