mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-21 02:33:07 +00:00
83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
190 lines
6.8 KiB
INI
190 lines
6.8 KiB
INI
# SPDX-License-Identifier: GPL-2.0+
|
|
#
|
|
# Copyright (C) 2011
|
|
# Stefan Herbrechtsmeier <stefan@herbrechtsmeier.net>
|
|
#
|
|
# Based on Kirkwood support:
|
|
# (C) Copyright 2009
|
|
# Marvell Semiconductor <www.marvell.com>
|
|
# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
|
|
# Refer doc/README.kwbimage for more details about how-to configure
|
|
# and create kirkwood boot image
|
|
#
|
|
|
|
# Boot Media configurations
|
|
BOOT_FROM nand
|
|
NAND_ECC_MODE default
|
|
NAND_PAGE_SIZE 0x0800
|
|
|
|
# SOC registers configuration using bootrom header extension
|
|
# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
|
|
|
|
# Configure RGMII-0 interface pad voltage to 1.8V
|
|
DATA 0xFFD100e0 0x1b1b1b9b
|
|
|
|
#Dram initalization for SINGLE x16 CL=5 @ 400MHz
|
|
DATA 0xFFD01400 0x43000c30 # DDR Configuration register
|
|
# bit13-0: 0xc30, 3120 DDR2 clks refresh rate
|
|
# bit23-14: 0 required
|
|
# bit24: 1, enable exit self refresh mode on DDR access
|
|
# bit25: 1 required
|
|
# bit29-26: 0 required
|
|
# bit31-30: 0b01 required
|
|
|
|
DATA 0xFFD01404 0x39543000 # DDR Controller Control Low
|
|
# bit3-0: 0 required
|
|
# bit4: 0, addr/cmd in smame cycle
|
|
# bit5: 0, clk is driven during self refresh, we don't care for APX
|
|
# bit6: 0, use recommended falling edge of clk for addr/cmd
|
|
# bit11-7: 0 required
|
|
# bit12: 1 required
|
|
# bit13: 1 required
|
|
# bit14: 0, input buffer always powered up
|
|
# bit17-15: 0 required
|
|
# bit18: 1, cpu lock transaction enabled
|
|
# bit19: 0 required
|
|
# bit23-20: 5, recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
|
|
# bit27-24: 9, CL+4, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
|
|
# bit30-28: 3 required
|
|
# bit31: 0, no additional STARTBURST delay
|
|
|
|
DATA 0xFFD01408 0x22125451 # DDR Timing (Low)
|
|
# bit3-0: 1, 18 cycle tRAS (tRAS[3-0])
|
|
# bit7-4: 5, 6 cycle tRCD
|
|
# bit11-8: 4, 5 cyle tRP
|
|
# bit15-12: 5, 6 cyle tWR
|
|
# bit19-16: 2, 3 cyle tWTR
|
|
# bit20: 1, 18 cycle tRAS (tRAS[4])
|
|
# bit23-21: 0 required
|
|
# bit27-24: 2, 3 cycle tRRD
|
|
# bit31-28: 2, 3 cyle tRTP
|
|
|
|
DATA 0xFFD0140C 0x00000833 # DDR Timing (High)
|
|
# bit6-0: 0x33, 33 cycle tRFC
|
|
# bit8-7: 0, 1 cycle tR2R
|
|
# bit10-9: 0, 1 cyle tR2W
|
|
# bit12-11: 1, 2 cylce tW2W
|
|
# bit31-13: 0 required
|
|
|
|
DATA 0xFFD01410 0x0000000c # DDR Address Control
|
|
# bit1-0: 0, Cs0width=x8
|
|
# bit3-2: 3, Cs0size=1Gb
|
|
# bit5-4: 0, Cs1width=nonexistent
|
|
# bit7-6: 0, Cs1size=nonexistent
|
|
# bit9-8: 0, Cs2width=nonexistent
|
|
# bit11-10: 0, Cs2size=nonexistent
|
|
# bit13-12: 0, Cs3width=nonexistent
|
|
# bit15-14: 0, Cs3size=nonexistent
|
|
# bit16: 0, Cs0AddrSel
|
|
# bit17: 0, Cs1AddrSel
|
|
# bit18: 0, Cs2AddrSel
|
|
# bit19: 0, Cs3AddrSel
|
|
# bit31-20: 0 required
|
|
|
|
DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
|
|
# bit0: 0, OPEn=OpenPage enabled
|
|
# bit31-1: 0 required
|
|
|
|
DATA 0xFFD01418 0x00000000 # DDR Operation
|
|
# bit3-0: 0, Cmd=Normal SDRAM Mode
|
|
# bit31-4: 0 required
|
|
|
|
DATA 0xFFD0141C 0x00000C52 # DDR Mode
|
|
# bit2-0: 2, Burst Length (2 required)
|
|
# bit3: 0, Burst Type (0 required)
|
|
# bit6-4: 5, CAS Latency (CL) 5
|
|
# bit7: 0, (Test Mode) Normal operation
|
|
# bit8: 0, (Reset DLL) Normal operation
|
|
# bit11-9: 0, Write recovery for auto-precharge (3 required ??)
|
|
# bit12: 0, Fast Active power down exit time (0 required)
|
|
# bit31-13: 0 required
|
|
|
|
DATA 0xFFD01420 0x00000040 # DDR Extended Mode
|
|
# bit0: 0, DRAM DLL enabled
|
|
# bit1: 0, DRAM drive strength normal
|
|
# bit2: 0, ODT control Rtt[0] (Rtt=2, 150 ohm termination)
|
|
# bit5-3: 0 required
|
|
# bit6: 1, ODT control Rtt[1] (Rtt=2, 150 ohm termination)
|
|
# bit9-7: 0 required
|
|
# bit10: 0, differential DQS enabled
|
|
# bit11: 0 required
|
|
# bit12: 0, DRAM output buffer enabled
|
|
# bit31-13: 0 required
|
|
|
|
DATA 0xFFD01424 0x0000F17F # DDR Controller Control High
|
|
# bit2-0: 0x7 required
|
|
# bit3: 1, MBUS Burst Chop disabled
|
|
# bit6-4: 0x7 required
|
|
# bit7: 0 required
|
|
# bit8: 1, add writepath sample stage, must be 1 for DDR freq >= 300MHz
|
|
# bit9: 0, no half clock cycle addition to dataout
|
|
# bit10: 0, 1/4 clock cycle skew enabled for addr/ctl signals
|
|
# bit11: 0, 1/4 clock cycle skew disabled for write mesh
|
|
# bit15-12: 0xf required
|
|
# bit31-16: 0 required
|
|
|
|
DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing
|
|
# bit3-0: 0 required
|
|
# bit7-4: 2, 2 cycles from read command to assertion of M_ODT signal
|
|
# bit11-8: 5, 5 cycles from read command to de-assertion of M_ODT signal
|
|
# bit15-12: 5, 5 cycles from read command to assertion of internal ODT signal
|
|
# bit19-16: 8, 8 cycles from read command to de-assertion of internal ODT signal
|
|
# bit31-20: 0 required
|
|
|
|
DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing
|
|
# bit3-0: 2, 2 cycles from write comand to assertion of M_ODT signal
|
|
# bit7-4: 5, 5 cycles from write command to de-assertion of M_ODT signal
|
|
# bit15-12: 5, 5 cycles from write command to assertion of internal ODT signal
|
|
# bit19-16: 8, 8 cycles from write command to de-assertion of internal ODT signal
|
|
# bit31-16: 0 required
|
|
|
|
DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0
|
|
DATA 0xFFD01504 0x0FFFFFF1 # CS[0]n Size
|
|
# bit0: 1, Window enabled
|
|
# bit1: 0, Write Protect disabled
|
|
# bit3-2: 0x0, CS0 hit selected
|
|
# bit23-4: 0xfffff required
|
|
# bit31-24: 0x0f, Size (i.e. 256MB)
|
|
|
|
DATA 0xFFD01508 0x10000000 # CS[1]n Base address to 256Mb
|
|
DATA 0xFFD0150C 0x0FFFFFF5 # CS[1]n Size 256Mb Window enabled for CS1
|
|
# bit0: 1, Window enabled
|
|
# bit1: 0, Write Protect disabled
|
|
# bit3-2: 1, CS1 hit selected
|
|
# bit23-4: 0xfffff required
|
|
# bit31-24: 0x0f, Size (i.e. 256MB)
|
|
|
|
DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled
|
|
DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled
|
|
|
|
DATA 0xFFD01494 0x00030000 # DDR ODT Control (Low)
|
|
# bit3-0: 0b0000, (read) M_ODT[0] is not asserted during read from DRAM
|
|
# bit7-4: 0b0000, (read) M_ODT[1] is not asserted during read from DRAM
|
|
# bit15-8: 0 required
|
|
# bit19-16: 0b0011, (write) M_ODT[0] is asserted during write to DRAM CS0 and CS1
|
|
# bit23-20: 0b0000, (write) M_ODT[1] is not asserted during write to DRAM
|
|
# bit31-24: 0 required
|
|
|
|
DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
|
|
# bit1-0: 0, M_ODT[0] assertion is controlled by ODT Control Low register
|
|
# bit3-2: 0, M_ODT[1] assertion is controlled by ODT Control Low register
|
|
# bit31-4 0 required
|
|
|
|
DATA 0xFFD0149C 0x0000E803 # CPU ODT Control
|
|
# bit3-0: 0b0011, internal ODT is asserted during read from DRAM bank 0-1
|
|
# bit7-4: 0b0000, internal ODT is not asserted during write to DRAM bank 0-4
|
|
# bit9-8: 0, Internal ODT assertion is controlled by fiels
|
|
# bit11-10: 2, M_DQ, M_DM, and M_DQS I/O buffer ODT 75 ohm
|
|
# bit13-12: 2, M_STARTBURST_IN I/O buffer ODT 75 ohm
|
|
# bit14: 1, M_STARTBURST_IN ODT enabled
|
|
# bit15: 1, DDR IO ODT Unit: Drive ODT calibration values
|
|
# bit20-16: 0, Pad N channel driving strength for ODT
|
|
# bit25-21: 0, Pad P channel driving strength for ODT
|
|
# bit31-26: 0 required
|
|
|
|
DATA 0xFFD01480 0x00000001 # DDR Initialization Control
|
|
# bit0: 1, enable DDR init upon this register write
|
|
# bit31-1: 0, required
|
|
|
|
# End of Header extension
|
|
DATA 0x0 0x0
|