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https://github.com/AsahiLinux/u-boot
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07679b1172
This patch adds Ethernet Switch support that found on R-Car S4 (r8a779f0) SoC. This is extracted from multiple patches from downstream BSP, with additional rework of the network device registration. Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Signed-off-by: Phong Hoang <phong.hoang.wz@renesas.com> Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> [Marek: Rework the driver to support all ports via subdrivers. Split the driver up, add generic PHY framework support. Generic code clean ups.] Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
1139 lines
28 KiB
C
1139 lines
28 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Driver for Renesas Ethernet RSwitch2 (Ethernet-TSN).
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*
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* Copyright (C) 2021 Renesas Electronics Corporation
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*
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* Based on the Renesas Ethernet AVB driver.
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*/
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#include <asm/io.h>
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#include <clk.h>
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#include <common.h>
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#include <dm.h>
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#include <dm/device-internal.h>
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#include <dm/device_compat.h>
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#include <dm/lists.h>
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#include <errno.h>
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#include <generic-phy.h>
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#include <linux/bitops.h>
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#include <linux/delay.h>
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#include <linux/iopoll.h>
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#include <linux/mii.h>
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#include <eth_phy.h>
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#include <log.h>
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#include <malloc.h>
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#include <miiphy.h>
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#define RSWITCH_SLEEP_US 1000
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#define RSWITCH_TIMEOUT_US 1000000
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#define RSWITCH_NUM_HW 5
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#define ETHA_TO_GWCA(i) ((i) % 2)
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#define GWCA_TO_HW_INDEX(i) ((i) + 3)
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#define HW_INDEX_TO_GWCA(i) ((i) - 3)
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#define RSWITCH_MAX_CTAG_PCP 7
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/* Registers */
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#define RSWITCH_COMA_OFFSET 0x00009000
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#define RSWITCH_ETHA_OFFSET 0x0000a000 /* with RMAC */
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#define RSWITCH_ETHA_SIZE 0x00002000 /* with RMAC */
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#define RSWITCH_GWCA_OFFSET 0x00010000
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#define RSWITCH_GWCA_SIZE 0x00002000
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#define FWRO 0
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#define CARO RSWITCH_COMA_OFFSET
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#define GWRO 0
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#define TARO 0
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#define RMRO 0x1000
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enum rswitch_reg {
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EAMC = TARO + 0x0000,
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EAMS = TARO + 0x0004,
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EATDQDC = TARO + 0x0060,
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EATTFC = TARO + 0x0138,
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EATASRIRM = TARO + 0x03E4,
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GWMC = GWRO + 0x0000,
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GWMS = GWRO + 0x0004,
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GWMTIRM = GWRO + 0x0100,
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GWVCC = GWRO + 0x0130,
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GWTTFC = GWRO + 0x0138,
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GWDCBAC0 = GWRO + 0x0194,
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GWDCBAC1 = GWRO + 0x0198,
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GWTRC = GWRO + 0x0200,
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GWARIRM = GWRO + 0x0380,
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GWDCC = GWRO + 0x0400,
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RRC = CARO + 0x0004,
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RCEC = CARO + 0x0008,
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RCDC = CARO + 0x000C,
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CABPIRM = CARO + 0x0140,
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FWPC0 = FWRO + 0x0100,
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FWPBFC = FWRO + 0x4A00,
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FWPBFCSDC = FWRO + 0x4A04,
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MPSM = RMRO + 0x0000,
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MPIC = RMRO + 0x0004,
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MRMAC0 = RMRO + 0x0084,
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MRMAC1 = RMRO + 0x0088,
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MRAFC = RMRO + 0x008C,
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MRSCE = RMRO + 0x0090,
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MRSCP = RMRO + 0x0094,
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MLVC = RMRO + 0x0180,
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MLBC = RMRO + 0x0188,
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MXGMIIC = RMRO + 0x0190,
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MPCH = RMRO + 0x0194,
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MANM = RMRO + 0x019C,
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MMIS0 = RMRO + 0x0210,
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MMIS1 = RMRO + 0x0220,
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};
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/* COMA */
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#define RRC_RR BIT(0)
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#define RCEC_RCE BIT(16)
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#define CABPIRM_BPIOG BIT(0)
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#define CABPIRM_BPR BIT(1)
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/* MFWD */
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#define FWPC0(i) (FWPC0 + (i) * 0x10)
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#define FWPC0_LTHTA BIT(0)
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#define FWPC0_IP4UE BIT(3)
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#define FWPC0_IP4TE BIT(4)
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#define FWPC0_IP4OE BIT(5)
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#define FWPC0_L2SE BIT(9)
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#define FWPC0_IP4EA BIT(10)
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#define FWPC0_IPDSA BIT(12)
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#define FWPC0_IPHLA BIT(18)
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#define FWPC0_MACSDA BIT(20)
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#define FWPC0_MACHLA BIT(26)
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#define FWPC0_MACHMA BIT(27)
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#define FWPC0_VLANSA BIT(28)
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#define FWPC0_DEFAULT (FWPC0_LTHTA | FWPC0_IP4UE | FWPC0_IP4TE | \
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FWPC0_IP4OE | FWPC0_L2SE | FWPC0_IP4EA | \
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FWPC0_IPDSA | FWPC0_IPHLA | FWPC0_MACSDA | \
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FWPC0_MACHLA | FWPC0_MACHMA | FWPC0_VLANSA)
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#define FWPBFC(i) (FWPBFC + (i) * 0x10)
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#define FWPBFCSDC(j, i) (FWPBFCSDC + (i) * 0x10 + (j) * 0x04)
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/* ETHA */
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#define EATASRIRM_TASRIOG BIT(0)
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#define EATASRIRM_TASRR BIT(1)
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#define EATDQDC(q) (EATDQDC + (q) * 0x04)
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#define EATDQDC_DQD (0xff)
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/* RMAC */
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#define MPIC_PIS_GMII 0x02
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#define MPIC_LSC_MASK (0x07 << 3)
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#define MPIC_LSC_100 (0x01 << 3)
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#define MPIC_LSC_1000 (0x02 << 3)
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#define MPIC_LSC_2500 (0x03 << 3)
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#define MLVC_PLV BIT(16)
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#define MLVC_LVT 0x09
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#define MMIS0_LVSS 0x02
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#define MPIC_PSMCS_MASK (0x7f << 16)
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#define MPIC_PSMHT_MASK (0x06 << 24)
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#define MPIC_MDC_CLK_SET (0x06050000)
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#define MPSM_MFF_C45 BIT(2)
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#define MPSM_MFF_C22 0x0
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#define MPSM_PSME BIT(0)
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#define MDIO_READ_C45 0x03
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#define MDIO_WRITE_C45 0x01
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#define MDIO_ADDR_C45 0x00
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#define MDIO_READ_C22 0x02
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#define MDIO_WRITE_C22 0x01
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#define MPSM_POP_MASK (0x03 << 13)
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#define MPSM_PRA_MASK (0x1f << 8)
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#define MPSM_PDA_MASK (0x1f << 3)
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#define MPSM_PRD_MASK (0xffff << 16)
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/* Completion flags */
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#define MMIS1_PAACS BIT(2) /* Address */
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#define MMIS1_PWACS BIT(1) /* Write */
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#define MMIS1_PRACS BIT(0) /* Read */
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#define MMIS1_CLEAR_FLAGS 0xf
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/* ETHA */
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enum rswitch_etha_mode {
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EAMC_OPC_RESET,
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EAMC_OPC_DISABLE,
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EAMC_OPC_CONFIG,
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EAMC_OPC_OPERATION,
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};
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#define EAMS_OPS_MASK EAMC_OPC_OPERATION
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/* GWCA */
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enum rswitch_gwca_mode {
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GWMC_OPC_RESET,
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GWMC_OPC_DISABLE,
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GWMC_OPC_CONFIG,
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GWMC_OPC_OPERATION,
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};
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#define GWMS_OPS_MASK GWMC_OPC_OPERATION
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#define GWMTIRM_MTIOG BIT(0)
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#define GWMTIRM_MTR BIT(1)
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#define GWARIRM_ARIOG BIT(0)
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#define GWARIRM_ARR BIT(1)
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#define GWVCC_VEM_SC_TAG (0x3 << 16)
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#define GWDCBAC0_DCBAUP (0xff)
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#define GWTRC(i) (GWTRC + (i) * 0x04)
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#define GWDCC(i) (GWDCC + (i) * 0x04)
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#define GWDCC_DQT BIT(11)
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#define GWDCC_BALR BIT(24)
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struct rswitch_etha {
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int index;
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void __iomem *addr;
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struct phy_device *phydev;
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struct mii_dev *bus;
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unsigned char *enetaddr;
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};
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struct rswitch_gwca {
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int index;
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void __iomem *addr;
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int num_chain;
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};
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/* Setting value */
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#define LINK_SPEED_100 100
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#define LINK_SPEED_1000 1000
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#define LINK_SPEED_2500 2500
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/* Decriptor */
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#define RSWITCH_NUM_BASE_DESC 2
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#define RSWITCH_TX_CHAIN_INDEX 0
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#define RSWITCH_RX_CHAIN_INDEX 1
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#define RSWITCH_NUM_TX_DESC 8
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#define RSWITCH_NUM_RX_DESC 8
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enum RX_DS_CC_BIT {
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RX_DS = 0x0fff, /* Data size */
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RX_TR = 0x1000, /* Truncation indication */
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RX_EI = 0x2000, /* Error indication */
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RX_PS = 0xc000, /* Padding selection */
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};
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enum DIE_DT {
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/* Frame data */
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DT_FSINGLE = 0x80,
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DT_FSTART = 0x90,
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DT_FMID = 0xa0,
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DT_FEND = 0xb8,
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/* Chain control */
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DT_LEMPTY = 0xc0,
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DT_EEMPTY = 0xd0,
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DT_LINKFIX = 0x00,
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DT_LINK = 0xe0,
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DT_EOS = 0xf0,
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/* HW/SW arbitration */
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DT_FEMPTY = 0x40,
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DT_FEMPTY_IS = 0x10,
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DT_FEMPTY_IC = 0x20,
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DT_FEMPTY_ND = 0x38,
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DT_FEMPTY_START = 0x50,
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DT_FEMPTY_MID = 0x60,
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DT_FEMPTY_END = 0x70,
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DT_MASK = 0xf0,
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DIE = 0x08, /* Descriptor Interrupt Enable */
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};
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struct rswitch_desc {
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__le16 info_ds; /* Descriptor size */
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u8 die_dt; /* Descriptor interrupt enable and type */
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__u8 dptrh; /* Descriptor pointer MSB */
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__le32 dptrl; /* Descriptor pointer LSW */
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} __packed;
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struct rswitch_rxdesc {
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struct rswitch_desc data;
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struct rswitch_desc link;
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u8 __pad[48];
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u8 packet[PKTSIZE_ALIGN];
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} __packed;
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struct rswitch_port_priv {
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void __iomem *addr;
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struct phy serdes;
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struct rswitch_etha etha;
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struct rswitch_gwca gwca;
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struct rswitch_desc bat_desc[RSWITCH_NUM_BASE_DESC];
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struct rswitch_desc tx_desc[RSWITCH_NUM_TX_DESC];
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struct rswitch_rxdesc rx_desc[RSWITCH_NUM_RX_DESC];
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u32 rx_desc_index;
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u32 tx_desc_index;
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};
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struct rswitch_priv {
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void __iomem *addr;
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struct clk *rsw_clk;
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};
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static inline void rswitch_flush_dcache(u32 addr, u32 len)
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{
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flush_dcache_range(addr, addr + len);
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}
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static inline void rswitch_invalidate_dcache(u32 addr, u32 len)
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{
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u32 start = addr & ~((uintptr_t)ARCH_DMA_MINALIGN - 1);
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u32 end = roundup(addr + len, ARCH_DMA_MINALIGN);
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invalidate_dcache_range(start, end);
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}
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static void rswitch_agent_clock_ctrl(struct rswitch_port_priv *priv, int port, int enable)
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{
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u32 val;
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if (enable) {
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val = readl(priv->addr + RCEC);
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if ((val & (RCEC_RCE | BIT(port))) != (RCEC_RCE | BIT(port)))
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writel(val | RCEC_RCE | BIT(port), priv->addr + RCEC);
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} else {
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setbits_le32(priv->addr + RCDC, BIT(port));
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}
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}
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static int rswitch_etha_change_mode(struct rswitch_port_priv *priv,
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enum rswitch_etha_mode mode)
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{
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struct rswitch_etha *etha = &priv->etha;
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u32 pval;
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int ret;
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/* Enable clock */
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rswitch_agent_clock_ctrl(priv, etha->index, 1);
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writel(mode, etha->addr + EAMC);
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ret = readl_poll_sleep_timeout(etha->addr + EAMS, pval,
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(pval & EAMS_OPS_MASK) == mode,
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RSWITCH_SLEEP_US, RSWITCH_TIMEOUT_US);
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/* Disable clock */
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if (mode == EAMC_OPC_DISABLE)
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rswitch_agent_clock_ctrl(priv, etha->index, 0);
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return ret;
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}
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static int rswitch_gwca_change_mode(struct rswitch_port_priv *priv,
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enum rswitch_gwca_mode mode)
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{
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struct rswitch_gwca *gwca = &priv->gwca;
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u32 pval;
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int ret;
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/* Enable clock */
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rswitch_agent_clock_ctrl(priv, gwca->index, 1);
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writel(mode, gwca->addr + GWMC);
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ret = readl_poll_sleep_timeout(gwca->addr + GWMS, pval,
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(pval & GWMS_OPS_MASK) == mode,
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RSWITCH_SLEEP_US, RSWITCH_TIMEOUT_US);
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/* Disable clock */
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if (mode == GWMC_OPC_DISABLE)
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rswitch_agent_clock_ctrl(priv, gwca->index, 0);
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return ret;
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}
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static int rswitch_mii_access_c45(struct rswitch_etha *etha, bool read,
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int phyad, int devad, int regad, int data)
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{
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u32 pval, val;
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int ret;
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/* No match device */
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if (devad == 0xffffffff)
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return 0;
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/* Clear completion flags */
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writel(MMIS1_CLEAR_FLAGS, etha->addr + MMIS1);
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/* Submit address to PHY (MDIO_ADDR_C45 << 13) */
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val = MPSM_PSME | MPSM_MFF_C45 | (devad << 8) | (phyad << 3);
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writel((regad << 16) | val, etha->addr + MPSM);
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ret = readl_poll_sleep_timeout(etha->addr + MMIS1, pval,
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pval & MMIS1_PAACS,
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RSWITCH_SLEEP_US, RSWITCH_TIMEOUT_US);
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if (ret)
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return ret;
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/* Clear address completion flag */
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setbits_le32(etha->addr + MMIS1, MMIS1_PAACS);
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/* Read/Write PHY register */
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if (read) {
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val |= MDIO_READ_C45 << 13;
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writel(val, etha->addr + MPSM);
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ret = readl_poll_sleep_timeout(etha->addr + MMIS1, pval,
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pval & MMIS1_PRACS,
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RSWITCH_SLEEP_US,
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RSWITCH_TIMEOUT_US);
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if (ret)
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return ret;
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/* Read data */
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ret = (readl(etha->addr + MPSM) & MPSM_PRD_MASK) >> 16;
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/* Clear read completion flag */
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setbits_le32(etha->addr + MMIS1, MMIS1_PRACS);
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} else {
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val |= MDIO_WRITE_C45 << 13;
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val |= data << 16;
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writel(val, etha->addr + MPSM);
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ret = readl_poll_sleep_timeout(etha->addr + MMIS1, pval,
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pval & MMIS1_PWACS,
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RSWITCH_SLEEP_US,
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RSWITCH_TIMEOUT_US);
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}
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return ret;
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}
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static int rswitch_mii_read_c45(struct mii_dev *miidev, int phyad, int devad, int regad)
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{
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struct rswitch_port_priv *priv = miidev->priv;
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struct rswitch_etha *etha = &priv->etha;
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int val;
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int reg;
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/* Change to disable mode */
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rswitch_etha_change_mode(priv, EAMC_OPC_DISABLE);
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/* Change to config mode */
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rswitch_etha_change_mode(priv, EAMC_OPC_CONFIG);
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/* Enable Station Management clock */
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reg = readl(etha->addr + MPIC);
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reg &= ~MPIC_PSMCS_MASK & ~MPIC_PSMHT_MASK;
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writel(reg | MPIC_MDC_CLK_SET, etha->addr + MPIC);
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/* Set Station Management Mode : Clause 45 */
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setbits_le32(etha->addr + MPSM, MPSM_MFF_C45);
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/* Access PHY register */
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val = rswitch_mii_access_c45(etha, true, phyad, devad, regad, 0);
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/* Disable Station Management Clock */
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clrbits_le32(etha->addr + MPIC, MPIC_PSMCS_MASK);
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/* Change to disable mode */
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rswitch_etha_change_mode(priv, EAMC_OPC_DISABLE);
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return val;
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}
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int rswitch_mii_write_c45(struct mii_dev *miidev, int phyad, int devad, int regad, u16 data)
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{
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struct rswitch_port_priv *priv = miidev->priv;
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struct rswitch_etha *etha = &priv->etha;
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int reg;
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/* Change to disable mode */
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rswitch_etha_change_mode(priv, EAMC_OPC_DISABLE);
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/* Change to config mode */
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rswitch_etha_change_mode(priv, EAMC_OPC_CONFIG);
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/* Enable Station Management clock */
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reg = readl(etha->addr + MPIC);
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reg &= ~MPIC_PSMCS_MASK & ~MPIC_PSMHT_MASK;
|
|
writel(reg | MPIC_MDC_CLK_SET, etha->addr + MPIC);
|
|
|
|
/* Set Station Management Mode : Clause 45 */
|
|
setbits_le32(etha->addr + MPSM, MPSM_MFF_C45);
|
|
|
|
/* Access PHY register */
|
|
rswitch_mii_access_c45(etha, false, phyad, devad, regad, data);
|
|
|
|
/* Disable Station Management Clock */
|
|
clrbits_le32(etha->addr + MPIC, MPIC_PSMCS_MASK);
|
|
|
|
/* Change to disable mode */
|
|
rswitch_etha_change_mode(priv, EAMC_OPC_DISABLE);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int rswitch_check_link(struct rswitch_etha *etha)
|
|
{
|
|
u32 pval;
|
|
int ret;
|
|
|
|
/* Request Link Verification */
|
|
writel(MLVC_PLV, etha->addr + MLVC);
|
|
|
|
/* Complete Link Verification */
|
|
ret = readl_poll_sleep_timeout(etha->addr + MLVC, pval,
|
|
!(pval & MLVC_PLV),
|
|
RSWITCH_SLEEP_US, RSWITCH_TIMEOUT_US);
|
|
if (ret) {
|
|
debug("\n%s: Link verification timeout!", __func__);
|
|
return ret;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int rswitch_reset(struct rswitch_port_priv *priv)
|
|
{
|
|
int ret;
|
|
|
|
setbits_le32(priv->addr + RRC, RRC_RR);
|
|
clrbits_le32(priv->addr + RRC, RRC_RR);
|
|
|
|
ret = rswitch_gwca_change_mode(priv, GWMC_OPC_DISABLE);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = rswitch_etha_change_mode(priv, EAMC_OPC_DISABLE);
|
|
if (ret)
|
|
return ret;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void rswitch_bat_desc_init(struct rswitch_port_priv *priv)
|
|
{
|
|
const u32 desc_size = RSWITCH_NUM_BASE_DESC * sizeof(struct rswitch_desc);
|
|
int i;
|
|
|
|
/* Initialize all descriptors */
|
|
memset(priv->bat_desc, 0x0, desc_size);
|
|
|
|
for (i = 0; i < RSWITCH_NUM_BASE_DESC; i++)
|
|
priv->bat_desc[i].die_dt = DT_EOS;
|
|
|
|
rswitch_flush_dcache((uintptr_t)priv->bat_desc, desc_size);
|
|
}
|
|
|
|
static void rswitch_tx_desc_init(struct rswitch_port_priv *priv)
|
|
{
|
|
const u32 desc_size = RSWITCH_NUM_TX_DESC * sizeof(struct rswitch_desc);
|
|
u64 tx_desc_addr;
|
|
int i;
|
|
|
|
/* Initialize all descriptor */
|
|
memset(priv->tx_desc, 0x0, desc_size);
|
|
priv->tx_desc_index = 0;
|
|
|
|
for (i = 0; i < RSWITCH_NUM_TX_DESC; i++)
|
|
priv->tx_desc[i].die_dt = DT_EEMPTY;
|
|
|
|
/* Mark the end of the descriptors */
|
|
priv->tx_desc[RSWITCH_NUM_TX_DESC - 1].die_dt = DT_LINKFIX;
|
|
tx_desc_addr = (uintptr_t)priv->tx_desc;
|
|
priv->tx_desc[RSWITCH_NUM_TX_DESC - 1].dptrl = lower_32_bits(tx_desc_addr);
|
|
priv->tx_desc[RSWITCH_NUM_TX_DESC - 1].dptrh = upper_32_bits(tx_desc_addr);
|
|
rswitch_flush_dcache(tx_desc_addr, desc_size);
|
|
|
|
/* Point the controller to the TX descriptor list */
|
|
priv->bat_desc[RSWITCH_TX_CHAIN_INDEX].die_dt = DT_LINKFIX;
|
|
priv->bat_desc[RSWITCH_TX_CHAIN_INDEX].dptrl = lower_32_bits(tx_desc_addr);
|
|
priv->bat_desc[RSWITCH_TX_CHAIN_INDEX].dptrh = upper_32_bits(tx_desc_addr);
|
|
rswitch_flush_dcache((uintptr_t)&priv->bat_desc[RSWITCH_TX_CHAIN_INDEX],
|
|
sizeof(struct rswitch_desc));
|
|
}
|
|
|
|
static void rswitch_rx_desc_init(struct rswitch_port_priv *priv)
|
|
{
|
|
const u32 desc_size = RSWITCH_NUM_RX_DESC * sizeof(struct rswitch_rxdesc);
|
|
int i;
|
|
u64 packet_addr;
|
|
u64 next_rx_desc_addr;
|
|
u64 rx_desc_addr;
|
|
|
|
/* Initialize all descriptor */
|
|
memset(priv->rx_desc, 0x0, desc_size);
|
|
priv->rx_desc_index = 0;
|
|
|
|
for (i = 0; i < RSWITCH_NUM_RX_DESC; i++) {
|
|
priv->rx_desc[i].data.die_dt = DT_EEMPTY;
|
|
priv->rx_desc[i].data.info_ds = PKTSIZE_ALIGN;
|
|
packet_addr = (uintptr_t)priv->rx_desc[i].packet;
|
|
priv->rx_desc[i].data.dptrl = lower_32_bits(packet_addr);
|
|
priv->rx_desc[i].data.dptrh = upper_32_bits(packet_addr);
|
|
|
|
priv->rx_desc[i].link.die_dt = DT_LINKFIX;
|
|
next_rx_desc_addr = (uintptr_t)&priv->rx_desc[i + 1];
|
|
priv->rx_desc[i].link.dptrl = lower_32_bits(next_rx_desc_addr);
|
|
priv->rx_desc[i].link.dptrh = upper_32_bits(next_rx_desc_addr);
|
|
}
|
|
|
|
/* Mark the end of the descriptors */
|
|
priv->rx_desc[RSWITCH_NUM_RX_DESC - 1].link.die_dt = DT_LINKFIX;
|
|
rx_desc_addr = (uintptr_t)priv->rx_desc;
|
|
priv->rx_desc[RSWITCH_NUM_RX_DESC - 1].link.dptrl = lower_32_bits(rx_desc_addr);
|
|
priv->rx_desc[RSWITCH_NUM_RX_DESC - 1].link.dptrh = upper_32_bits(rx_desc_addr);
|
|
rswitch_flush_dcache(rx_desc_addr, desc_size);
|
|
|
|
/* Point the controller to the rx descriptor list */
|
|
priv->bat_desc[RSWITCH_RX_CHAIN_INDEX].die_dt = DT_LINKFIX;
|
|
priv->bat_desc[RSWITCH_RX_CHAIN_INDEX].dptrl = lower_32_bits(rx_desc_addr);
|
|
priv->bat_desc[RSWITCH_RX_CHAIN_INDEX].dptrh = upper_32_bits(rx_desc_addr);
|
|
rswitch_flush_dcache((uintptr_t)&priv->bat_desc[RSWITCH_RX_CHAIN_INDEX],
|
|
sizeof(struct rswitch_desc));
|
|
}
|
|
|
|
static void rswitch_clock_enable(struct rswitch_port_priv *priv)
|
|
{
|
|
struct rswitch_etha *etha = &priv->etha;
|
|
struct rswitch_gwca *gwca = &priv->gwca;
|
|
|
|
setbits_le32(priv->addr + RCEC, BIT(etha->index) | BIT(gwca->index) | RCEC_RCE);
|
|
}
|
|
|
|
static int rswitch_bpool_init(struct rswitch_port_priv *priv)
|
|
{
|
|
u32 pval;
|
|
|
|
writel(CABPIRM_BPIOG, priv->addr + CABPIRM);
|
|
|
|
return readl_poll_sleep_timeout(priv->addr + CABPIRM, pval,
|
|
pval & CABPIRM_BPR,
|
|
RSWITCH_SLEEP_US, RSWITCH_TIMEOUT_US);
|
|
}
|
|
|
|
static void rswitch_mfwd_init(struct rswitch_port_priv *priv)
|
|
{
|
|
struct rswitch_etha *etha = &priv->etha;
|
|
struct rswitch_gwca *gwca = &priv->gwca;
|
|
|
|
writel(FWPC0_DEFAULT, priv->addr + FWPC0(etha->index));
|
|
writel(FWPC0_DEFAULT, priv->addr + FWPC0(gwca->index));
|
|
|
|
writel(RSWITCH_RX_CHAIN_INDEX,
|
|
priv->addr + FWPBFCSDC(HW_INDEX_TO_GWCA(gwca->index), etha->index));
|
|
|
|
writel(BIT(gwca->index),
|
|
priv->addr + FWPBFC(etha->index));
|
|
|
|
writel(BIT(etha->index),
|
|
priv->addr + FWPBFC(gwca->index));
|
|
}
|
|
|
|
static void rswitch_rmac_init(struct rswitch_etha *etha)
|
|
{
|
|
unsigned char *mac = etha->enetaddr;
|
|
|
|
/* Set MAC address */
|
|
writel((mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5],
|
|
etha->addr + MRMAC1);
|
|
|
|
writel((mac[0] << 8) | mac[1], etha->addr + MRMAC0);
|
|
|
|
/* Set MIIx */
|
|
writel(MPIC_PIS_GMII | MPIC_LSC_1000, etha->addr + MPIC);
|
|
|
|
writel(0x07E707E7, etha->addr + MRAFC);
|
|
}
|
|
|
|
static int rswitch_gwca_mcast_table_reset(struct rswitch_gwca *gwca)
|
|
{
|
|
u32 pval;
|
|
|
|
writel(GWMTIRM_MTIOG, gwca->addr + GWMTIRM);
|
|
|
|
return readl_poll_sleep_timeout(gwca->addr + GWMTIRM, pval,
|
|
pval & GWMTIRM_MTR,
|
|
RSWITCH_SLEEP_US, RSWITCH_TIMEOUT_US);
|
|
}
|
|
|
|
static int rswitch_gwca_axi_ram_reset(struct rswitch_gwca *gwca)
|
|
{
|
|
u32 pval;
|
|
|
|
writel(GWARIRM_ARIOG, gwca->addr + GWARIRM);
|
|
|
|
return readl_poll_sleep_timeout(gwca->addr + GWARIRM, pval,
|
|
pval & GWARIRM_ARR,
|
|
RSWITCH_SLEEP_US, RSWITCH_TIMEOUT_US);
|
|
}
|
|
|
|
static int rswitch_gwca_init(struct rswitch_port_priv *priv)
|
|
{
|
|
struct rswitch_gwca *gwca = &priv->gwca;
|
|
int ret;
|
|
|
|
ret = rswitch_gwca_change_mode(priv, GWMC_OPC_DISABLE);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = rswitch_gwca_change_mode(priv, GWMC_OPC_CONFIG);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = rswitch_gwca_mcast_table_reset(gwca);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = rswitch_gwca_axi_ram_reset(gwca);
|
|
if (ret)
|
|
return ret;
|
|
|
|
/* Setting flow */
|
|
writel(GWVCC_VEM_SC_TAG, gwca->addr + GWVCC);
|
|
writel(0, gwca->addr + GWTTFC);
|
|
writel(upper_32_bits((uintptr_t)priv->bat_desc) & GWDCBAC0_DCBAUP, gwca->addr + GWDCBAC0);
|
|
writel(lower_32_bits((uintptr_t)priv->bat_desc), gwca->addr + GWDCBAC1);
|
|
writel(GWDCC_DQT | GWDCC_BALR, gwca->addr + GWDCC(RSWITCH_TX_CHAIN_INDEX));
|
|
writel(GWDCC_BALR, gwca->addr + GWDCC(RSWITCH_RX_CHAIN_INDEX));
|
|
|
|
ret = rswitch_gwca_change_mode(priv, GWMC_OPC_DISABLE);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = rswitch_gwca_change_mode(priv, GWMC_OPC_OPERATION);
|
|
if (ret)
|
|
return ret;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int rswitch_etha_tas_ram_reset(struct rswitch_etha *etha)
|
|
{
|
|
u32 pval;
|
|
|
|
writel(EATASRIRM_TASRIOG, etha->addr + EATASRIRM);
|
|
|
|
return readl_poll_sleep_timeout(etha->addr + EATASRIRM, pval,
|
|
pval & EATASRIRM_TASRR,
|
|
RSWITCH_SLEEP_US, RSWITCH_TIMEOUT_US);
|
|
}
|
|
|
|
static int rswitch_etha_init(struct rswitch_port_priv *priv)
|
|
{
|
|
struct rswitch_etha *etha = &priv->etha;
|
|
int ret;
|
|
u32 prio;
|
|
|
|
ret = rswitch_etha_change_mode(priv, EAMC_OPC_DISABLE);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = rswitch_etha_change_mode(priv, EAMC_OPC_CONFIG);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = rswitch_etha_tas_ram_reset(etha);
|
|
if (ret)
|
|
return ret;
|
|
|
|
/* Setting flow */
|
|
writel(0, etha->addr + EATTFC);
|
|
|
|
for (prio = 0; prio < RSWITCH_MAX_CTAG_PCP; prio++)
|
|
writel(EATDQDC_DQD, etha->addr + EATDQDC(prio));
|
|
|
|
rswitch_rmac_init(etha);
|
|
|
|
ret = rswitch_etha_change_mode(priv, EAMC_OPC_OPERATION);
|
|
if (ret)
|
|
return ret;
|
|
|
|
/* Link Verification */
|
|
ret = rswitch_check_link(etha);
|
|
if (ret)
|
|
return ret;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int rswitch_init(struct rswitch_port_priv *priv)
|
|
{
|
|
struct rswitch_etha *etha = &priv->etha;
|
|
int ret;
|
|
|
|
ret = rswitch_reset(priv);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = generic_phy_set_mode(&priv->serdes, PHY_MODE_ETHERNET,
|
|
etha->phydev->interface);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = generic_phy_set_speed(&priv->serdes, etha->phydev->speed);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = generic_phy_init(&priv->serdes);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = generic_phy_power_on(&priv->serdes);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = phy_startup(etha->phydev);
|
|
if (ret)
|
|
return ret;
|
|
|
|
rswitch_bat_desc_init(priv);
|
|
rswitch_tx_desc_init(priv);
|
|
rswitch_rx_desc_init(priv);
|
|
|
|
rswitch_clock_enable(priv);
|
|
|
|
ret = rswitch_bpool_init(priv);
|
|
if (ret)
|
|
return ret;
|
|
|
|
rswitch_mfwd_init(priv);
|
|
|
|
ret = rswitch_gwca_init(priv);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = rswitch_etha_init(priv);
|
|
if (ret)
|
|
return ret;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int rswitch_start(struct udevice *dev)
|
|
{
|
|
struct rswitch_port_priv *priv = dev_get_priv(dev);
|
|
int ret;
|
|
|
|
ret = rswitch_init(priv);
|
|
if (ret)
|
|
return ret;
|
|
|
|
return 0;
|
|
}
|
|
|
|
#define RSWITCH_TX_TIMEOUT_MS 1000
|
|
static int rswitch_send(struct udevice *dev, void *packet, int len)
|
|
{
|
|
struct rswitch_port_priv *priv = dev_get_priv(dev);
|
|
struct rswitch_desc *desc = &priv->tx_desc[priv->tx_desc_index];
|
|
struct rswitch_gwca *gwca = &priv->gwca;
|
|
u32 gwtrc_index, start;
|
|
|
|
/* Update TX descriptor */
|
|
rswitch_flush_dcache((uintptr_t)packet, len);
|
|
memset(desc, 0x0, sizeof(*desc));
|
|
desc->die_dt = DT_FSINGLE;
|
|
desc->info_ds = len;
|
|
desc->dptrl = lower_32_bits((uintptr_t)packet);
|
|
desc->dptrh = upper_32_bits((uintptr_t)packet);
|
|
rswitch_flush_dcache((uintptr_t)desc, sizeof(*desc));
|
|
|
|
/* Start transmission */
|
|
gwtrc_index = RSWITCH_TX_CHAIN_INDEX / 32;
|
|
setbits_le32(gwca->addr + GWTRC(gwtrc_index), BIT(RSWITCH_TX_CHAIN_INDEX));
|
|
|
|
/* Wait until packet is transmitted */
|
|
start = get_timer(0);
|
|
while (get_timer(start) < RSWITCH_TX_TIMEOUT_MS) {
|
|
rswitch_invalidate_dcache((uintptr_t)desc, sizeof(*desc));
|
|
if ((desc->die_dt & DT_MASK) != DT_FSINGLE)
|
|
break;
|
|
udelay(10);
|
|
}
|
|
|
|
if (get_timer(start) >= RSWITCH_TX_TIMEOUT_MS) {
|
|
dev_dbg(dev, "\n%s: Timeout", __func__);
|
|
return -ETIMEDOUT;
|
|
}
|
|
|
|
priv->tx_desc_index = (priv->tx_desc_index + 1) % (RSWITCH_NUM_TX_DESC - 1);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int rswitch_recv(struct udevice *dev, int flags, uchar **packetp)
|
|
{
|
|
struct rswitch_port_priv *priv = dev_get_priv(dev);
|
|
struct rswitch_rxdesc *desc = &priv->rx_desc[priv->rx_desc_index];
|
|
u8 *packet;
|
|
int len;
|
|
|
|
/* Check if the rx descriptor is ready */
|
|
rswitch_invalidate_dcache((uintptr_t)desc, sizeof(*desc));
|
|
if ((desc->data.die_dt & DT_MASK) == DT_FEMPTY)
|
|
return -EAGAIN;
|
|
|
|
len = desc->data.info_ds & RX_DS;
|
|
packet = (u8 *)(((uintptr_t)(desc->data.dptrh) << 32) | (uintptr_t)desc->data.dptrl);
|
|
rswitch_invalidate_dcache((uintptr_t)packet, len);
|
|
|
|
*packetp = packet;
|
|
|
|
return len;
|
|
}
|
|
|
|
static int rswitch_free_pkt(struct udevice *dev, uchar *packet, int length)
|
|
{
|
|
struct rswitch_port_priv *priv = dev_get_priv(dev);
|
|
struct rswitch_rxdesc *desc = &priv->rx_desc[priv->rx_desc_index];
|
|
|
|
/* Make current descritor available again */
|
|
desc->data.die_dt = DT_FEMPTY;
|
|
desc->data.info_ds = PKTSIZE_ALIGN;
|
|
rswitch_flush_dcache((uintptr_t)desc, sizeof(*desc));
|
|
|
|
/* Point to the next descriptor */
|
|
priv->rx_desc_index = (priv->rx_desc_index + 1) % RSWITCH_NUM_RX_DESC;
|
|
desc = &priv->rx_desc[priv->rx_desc_index];
|
|
rswitch_invalidate_dcache((uintptr_t)desc, sizeof(*desc));
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void rswitch_stop(struct udevice *dev)
|
|
{
|
|
struct rswitch_port_priv *priv = dev_get_priv(dev);
|
|
|
|
phy_shutdown(priv->etha.phydev);
|
|
|
|
generic_phy_power_off(&priv->serdes);
|
|
}
|
|
|
|
static int rswitch_write_hwaddr(struct udevice *dev)
|
|
{
|
|
struct rswitch_port_priv *priv = dev_get_priv(dev);
|
|
struct rswitch_etha *etha = &priv->etha;
|
|
struct eth_pdata *pdata = dev_get_plat(dev);
|
|
unsigned char *mac = pdata->enetaddr;
|
|
|
|
writel((mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5],
|
|
etha->addr + MRMAC1);
|
|
|
|
writel((mac[0] << 8) | mac[1], etha->addr + MRMAC0);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int rswitch_phy_config(struct udevice *dev)
|
|
{
|
|
struct rswitch_port_priv *priv = dev_get_priv(dev);
|
|
struct rswitch_etha *etha = &priv->etha;
|
|
struct eth_pdata *pdata = dev_get_plat(dev);
|
|
struct phy_device *phydev;
|
|
int phy_addr;
|
|
|
|
phy_addr = eth_phy_get_addr(dev);
|
|
if (phy_addr < 0)
|
|
return phy_addr;
|
|
|
|
phydev = phy_connect(etha->bus, phy_addr, dev, pdata->phy_interface);
|
|
if (!phydev)
|
|
return -ENODEV;
|
|
|
|
etha->phydev = phydev;
|
|
phydev->speed = SPEED_1000;
|
|
|
|
phy_config(phydev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int rswitch_port_probe(struct udevice *dev)
|
|
{
|
|
struct rswitch_priv *rpriv =
|
|
(struct rswitch_priv *)dev_get_driver_data(dev);
|
|
struct eth_pdata *pdata = dev_get_plat(dev);
|
|
struct rswitch_port_priv *priv = dev_get_priv(dev);
|
|
struct rswitch_etha *etha = &priv->etha;
|
|
struct rswitch_gwca *gwca = &priv->gwca;
|
|
struct mii_dev *mdiodev;
|
|
int ret;
|
|
|
|
priv->addr = rpriv->addr;
|
|
|
|
etha->enetaddr = pdata->enetaddr;
|
|
|
|
etha->index = dev_read_u32_default(dev, "reg", 0);
|
|
etha->addr = priv->addr + RSWITCH_ETHA_OFFSET + etha->index * RSWITCH_ETHA_SIZE;
|
|
|
|
gwca->index = 1;
|
|
gwca->addr = priv->addr + RSWITCH_GWCA_OFFSET + gwca->index * RSWITCH_GWCA_SIZE;
|
|
gwca->index = GWCA_TO_HW_INDEX(gwca->index);
|
|
|
|
ret = generic_phy_get_by_index(dev, 0, &priv->serdes);
|
|
if (ret)
|
|
return ret;
|
|
|
|
/* Toggle the reset so we can access the PHYs */
|
|
ret = rswitch_reset(priv);
|
|
if (ret)
|
|
return ret;
|
|
|
|
mdiodev = mdio_alloc();
|
|
if (!mdiodev)
|
|
return -ENOMEM;
|
|
|
|
mdiodev->priv = priv;
|
|
mdiodev->read = rswitch_mii_read_c45;
|
|
mdiodev->write = rswitch_mii_write_c45;
|
|
snprintf(mdiodev->name, sizeof(mdiodev->name), dev->name);
|
|
|
|
ret = mdio_register(mdiodev);
|
|
if (ret)
|
|
goto err_mdio_register;
|
|
|
|
priv->etha.bus = miiphy_get_dev_by_name(dev->name);
|
|
|
|
ret = rswitch_phy_config(dev);
|
|
if (ret)
|
|
goto err_mdio_register;
|
|
|
|
return 0;
|
|
|
|
err_mdio_register:
|
|
mdio_free(mdiodev);
|
|
return ret;
|
|
}
|
|
|
|
static int rswitch_port_remove(struct udevice *dev)
|
|
{
|
|
struct rswitch_port_priv *priv = dev_get_priv(dev);
|
|
|
|
mdio_unregister(priv->etha.bus);
|
|
free(priv->etha.phydev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
int rswitch_ofdata_to_platdata(struct udevice *dev)
|
|
{
|
|
struct eth_pdata *pdata = dev_get_plat(dev);
|
|
|
|
pdata->phy_interface = dev_read_phy_mode(dev);
|
|
if (pdata->phy_interface == PHY_INTERFACE_MODE_NA)
|
|
return -EINVAL;
|
|
|
|
pdata->max_speed = dev_read_u32_default(dev, "max-speed", 1000);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct eth_ops rswitch_port_ops = {
|
|
.start = rswitch_start,
|
|
.send = rswitch_send,
|
|
.recv = rswitch_recv,
|
|
.free_pkt = rswitch_free_pkt,
|
|
.stop = rswitch_stop,
|
|
.write_hwaddr = rswitch_write_hwaddr,
|
|
};
|
|
|
|
U_BOOT_DRIVER(rswitch_port) = {
|
|
.name = "rswitch-port",
|
|
.id = UCLASS_ETH,
|
|
.of_to_plat = rswitch_ofdata_to_platdata,
|
|
.probe = rswitch_port_probe,
|
|
.remove = rswitch_port_remove,
|
|
.ops = &rswitch_port_ops,
|
|
.priv_auto = sizeof(struct rswitch_port_priv),
|
|
.plat_auto = sizeof(struct eth_pdata),
|
|
.flags = DM_FLAG_ALLOC_PRIV_DMA | DM_FLAG_OS_PREPARE,
|
|
};
|
|
|
|
static int rswitch_probe(struct udevice *dev)
|
|
{
|
|
struct rswitch_priv *priv = dev_get_plat(dev);
|
|
fdt_addr_t secure_base;
|
|
fdt_size_t size;
|
|
int ret;
|
|
|
|
secure_base = dev_read_addr_size_name(dev, "secure_base", &size);
|
|
if (!secure_base)
|
|
return -EINVAL;
|
|
|
|
priv->addr = map_physmem(secure_base, size, MAP_NOCACHE);
|
|
if (!priv->addr)
|
|
return -EINVAL;
|
|
|
|
priv->rsw_clk = devm_clk_get(dev, NULL);
|
|
if (ret)
|
|
goto err_map;
|
|
|
|
ret = clk_prepare_enable(priv->rsw_clk);
|
|
if (ret)
|
|
goto err_map;
|
|
|
|
return 0;
|
|
|
|
err_map:
|
|
unmap_physmem(priv->addr, MAP_NOCACHE);
|
|
return ret;
|
|
}
|
|
|
|
static int rswitch_remove(struct udevice *dev)
|
|
{
|
|
struct rswitch_priv *priv = dev_get_plat(dev);
|
|
|
|
clk_disable_unprepare(priv->rsw_clk);
|
|
unmap_physmem(priv->addr, MAP_NOCACHE);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int rswitch_bind(struct udevice *parent)
|
|
{
|
|
struct rswitch_port_priv *priv = dev_get_plat(parent);
|
|
ofnode ports_np, node;
|
|
struct udevice *dev;
|
|
struct driver *drv;
|
|
int ret;
|
|
|
|
drv = lists_driver_lookup_name("rswitch-port");
|
|
if (!drv)
|
|
return -ENOENT;
|
|
|
|
ports_np = dev_read_subnode(parent, "ethernet-ports");
|
|
if (!ofnode_valid(ports_np))
|
|
return -ENOENT;
|
|
|
|
ofnode_for_each_subnode(node, ports_np) {
|
|
ret = device_bind_with_driver_data(parent, drv,
|
|
ofnode_get_name(node),
|
|
(ulong)priv, node, &dev);
|
|
if (ret)
|
|
return ret;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct udevice_id rswitch_ids[] = {
|
|
{ .compatible = "renesas,r8a779f0-ether-switch" },
|
|
{ }
|
|
};
|
|
|
|
U_BOOT_DRIVER(rswitch) = {
|
|
.name = "rswitch",
|
|
.id = UCLASS_NOP,
|
|
.of_match = rswitch_ids,
|
|
.bind = rswitch_bind,
|
|
.probe = rswitch_probe,
|
|
.remove = rswitch_remove,
|
|
.plat_auto = sizeof(struct rswitch_priv),
|
|
};
|