mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-09-23 16:11:54 +00:00
6e38e2ea79
In all the ZynqMP boards dts files tx-buswidth is by default set to 1. Due to this the framework only issues 1-1-1 write commands to the GQSPI driver. But the GQSPI controller is capable of handling 1-4-4 write commands, so updated the tx-buswidth to 4 in ZynqMP boards dts files. This would enable the spi-nor framework to issue 1-4-4 write commands instead of 1-1-1. This will increase the tx data transfer rate, as now the tx data will be transferred on four lines instead on single line. Signed-off-by: Amit Kumar Mahapatra <amit.kumar-mahapatra@xilinx.com> Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/ad61199f55e5e00f29de6206d9d1872a52a7657e.1652193179.git.michal.simek@amd.com
79 lines
1.4 KiB
Text
79 lines
1.4 KiB
Text
// SPDX-License-Identifier: GPL-2.0+
|
|
/*
|
|
* dts file for Xilinx ZynqMP Mini Configuration
|
|
*
|
|
* (C) Copyright 2015 - 2020, Xilinx, Inc.
|
|
*
|
|
* Siva Durga Prasad <siva.durga.paladugu@xilinx.com>
|
|
* Michal Simek <michal.simek@xilinx.com>
|
|
*/
|
|
|
|
/dts-v1/;
|
|
|
|
/ {
|
|
model = "ZynqMP MINI QSPI";
|
|
compatible = "xlnx,zynqmp";
|
|
#address-cells = <2>;
|
|
#size-cells = <1>;
|
|
|
|
aliases {
|
|
serial0 = &dcc;
|
|
spi0 = &qspi;
|
|
};
|
|
|
|
chosen {
|
|
stdout-path = "serial0:115200n8";
|
|
};
|
|
|
|
memory@fffc0000 {
|
|
device_type = "memory";
|
|
reg = <0x0 0xfffc0000 0x40000>;
|
|
};
|
|
|
|
dcc: dcc {
|
|
compatible = "arm,dcc";
|
|
status = "disabled";
|
|
u-boot,dm-pre-reloc;
|
|
};
|
|
|
|
amba: amba {
|
|
compatible = "simple-bus";
|
|
#address-cells = <2>;
|
|
#size-cells = <1>;
|
|
ranges;
|
|
|
|
qspi: spi@ff0f0000 {
|
|
compatible = "xlnx,zynqmp-qspi-1.0";
|
|
status = "disabled";
|
|
clock-names = "ref_clk", "pclk";
|
|
clocks = <&misc_clk &misc_clk>;
|
|
num-cs = <1>;
|
|
reg = <0x0 0xff0f0000 0x1000 0x0 0xc0000000 0x8000000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
|
|
misc_clk: misc_clk {
|
|
compatible = "fixed-clock";
|
|
#clock-cells = <0>;
|
|
clock-frequency = <125000000>;
|
|
};
|
|
};
|
|
};
|
|
|
|
&qspi {
|
|
status = "okay";
|
|
flash0: flash@0 {
|
|
compatible = "n25q512a11", "jedec,spi-nor";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
reg = <0x0>;
|
|
spi-tx-bus-width = <4>;
|
|
spi-rx-bus-width = <4>;
|
|
spi-max-frequency = <40000000>;
|
|
};
|
|
};
|
|
|
|
&dcc {
|
|
status = "okay";
|
|
};
|