u-boot/arch/arm/mach-socfpga
Andre Przywara 5ff4857d35 armv8: Fix and simplify branch_if_master/branch_if_slave
The branch_if_master macro jumps to a label if the CPU is the "master"
core, which we define as having all affinity levels set to 0. To check
for this condition, we need to mask off some bits from the MPIDR
register, then compare the remaining register value against zero.

The implementation of this was slighly broken (it preserved the upper
RES0 bits), overly complicated and hard to understand, especially since
it lacked comments. The same was true for the very similar
branch_if_slave macro.

Use a much shorter assembly sequence for those checks, use the same
masking for both macros (just negate the final branch), and put some
comments on them, to make it clear what the code does.
This allows to drop the second temporary register for branch_if_master,
so we adjust all call sites as well.

Also use the opportunity to remove a misleading comment: the macro
works fine on SoCs with multiple clusters. Judging by the commit
message, the original problem with the Juno SoC stems from the fact that
the master CPU *can* be configured to be from cluster 1, so the
assumption that the master CPU has all affinity values set to 0 does not
hold there. But this is already mentioned above in a comment, so remove
the extra comment.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-03-02 13:59:29 -05:00
..
include/mach arm: socfpga: arria10: Enable double peripheral RBF configuration 2021-12-17 12:58:01 +08:00
board.c arm: socfpga: Move linux_qspi_enable from bootcommand to board_prep_linux function 2021-08-24 14:29:50 +08:00
clock_manager.c arm: socfpga: Changed to store QSPI reference clock in kHz 2021-04-08 17:29:12 +08:00
clock_manager_agilex.c arm: socfpga: Move Stratix10 and Agilex clock manager common code 2021-04-08 17:29:12 +08:00
clock_manager_arria10.c common: Drop linux/delay.h from common header 2020-05-18 21:19:23 -04:00
clock_manager_gen5.c arm: socfpga: Convert clock manager from struct to defines 2020-01-07 14:38:33 +01:00
clock_manager_n5x.c arm: socfpga: Add clock manager for Intel N5X device 2021-08-25 13:32:50 +08:00
clock_manager_s10.c arm: socfpga: Move Stratix10 and Agilex clock manager common code 2021-04-08 17:29:12 +08:00
firewall.c arm: socfpga: Move Stratix10 and Agilex system manager common code 2020-01-07 14:38:33 +01:00
fpga_manager.c SPDX: Convert all of our single license tags to Linux Kernel style 2018-05-07 09:34:12 -04:00
freeze_controller.c common: Drop linux/delay.h from common header 2020-05-18 21:19:23 -04:00
Kconfig lib: Drop SHA512_ALGO in lieu of SHA512 2021-09-08 16:11:46 -04:00
lowlevel_init_soc64.S armv8: Fix and simplify branch_if_master/branch_if_slave 2022-03-02 13:59:29 -05:00
mailbox_s10.c arm: socfpga: Changed to store QSPI reference clock in kHz 2021-04-08 17:29:12 +08:00
Makefile arm: socfpga: Enable Intel N5X device build 2021-08-25 15:26:38 +08:00
misc.c arm: socfpga: Get clock manager base address for Intel N5X device 2021-08-25 12:54:37 +08:00
misc_arria10.c arm: socfpga: arria10: Enable double peripheral RBF configuration 2021-12-17 12:58:01 +08:00
misc_gen5.c common: Drop asm/global_data.h from common header 2021-02-02 15:33:42 -05:00
misc_soc64.c arm: socfpga: Changed misc_s10.c to misc_soc64.c 2021-08-25 13:37:01 +08:00
mmu-arm64_s10.c common: Drop asm/global_data.h from common header 2021-02-02 15:33:42 -05:00
pinmux_arria10.c common: Drop log.h from common header 2020-05-18 21:19:18 -04:00
qts-filter-a10.sh arm: socfpga: arria10: Add qts-filter for Arria10 socfpga 2020-10-09 17:53:14 +08:00
qts-filter.sh ddr: altera: Add DDR2 support to Gen5 driver 2020-02-05 03:01:57 +01:00
reset_manager_arria10.c common: Drop asm/global_data.h from common header 2021-02-02 15:33:42 -05:00
reset_manager_gen5.c common: Drop linux/bitops.h from common header 2020-05-18 21:19:23 -04:00
reset_manager_s10.c common: Drop asm/global_data.h from common header 2021-02-02 15:33:42 -05:00
scan_manager.c common: Drop linux/delay.h from common header 2020-05-18 21:19:23 -04:00
secure_reg_helper.c arm: socfpga: Add secure register access helper functions for SoC 64bits 2021-01-15 17:48:36 +08:00
secure_vab.c arm: socfpga: soc64: Support Vendor Authorized Boot (VAB) 2021-03-08 10:59:10 +08:00
smc_api.c arm: socfpga: smc: Add function to get usercode 2021-04-08 17:29:13 +08:00
spl_a10.c arm: socfpga: arria10: Enable double peripheral RBF configuration 2021-12-17 12:58:01 +08:00
spl_agilex.c arm: socfpga: Move Stratix10 and Agilex SPL common code 2021-04-08 17:29:11 +08:00
spl_gen5.c mmc: Rename MMC_SUPPORT to MMC 2021-09-04 11:42:41 -04:00
spl_n5x.c arm: socfpga: Add SPL for Intel N5X device 2021-08-25 14:43:29 +08:00
spl_s10.c arm: socfpga: Move Stratix10 and Agilex SPL common code 2021-04-08 17:29:11 +08:00
spl_soc64.c mmc: Rename MMC_SUPPORT to MMC 2021-09-04 11:42:41 -04:00
system_manager_gen5.c arm: socfpga: Convert system manager from struct to defines 2020-01-07 14:38:33 +01:00
system_manager_soc64.c arm: socfpga: Add handoff data support for Intel N5X device 2021-08-24 17:13:35 +08:00
timer.c common: Drop init.h from common header 2020-05-18 17:33:33 -04:00
timer_s10.c arm: socfpga: soc64: Initialize timer in SPL only 2020-10-09 17:53:11 +08:00
vab.c global: Convert simple_strtoul() with hex to hextoul() 2021-08-02 13:32:14 -04:00
wrap_handoff_soc64.c arm: socfpga: Add handoff data support for Intel N5X device 2021-08-24 17:13:35 +08:00
wrap_iocsr_config.c SPDX: Convert all of our single license tags to Linux Kernel style 2018-05-07 09:34:12 -04:00
wrap_pinmux_config.c SPDX: Convert all of our single license tags to Linux Kernel style 2018-05-07 09:34:12 -04:00
wrap_pll_config.c SPDX: Convert all of our single license tags to Linux Kernel style 2018-05-07 09:34:12 -04:00
wrap_pll_config_soc64.c arm: socfpga: Changed wrap_pll_config_s10.c to wrap_pll_config_soc64.c 2021-04-08 17:29:12 +08:00
wrap_sdram_config.c ddr: altera: Add DDR2 support to Gen5 driver 2020-02-05 03:01:57 +01:00