mirror of
https://github.com/AsahiLinux/u-boot
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5d97fe2a04
TPL is introduced in the patch "NAND: TPL : introduce the TPL based on the SPL", here enable TPL for p1022ds nand boot. Signed-off-by: Ying Zhang <b40530@freescale.com> Acked-by: York Sun <yorksun@freescale.com>
71 lines
1.7 KiB
C
71 lines
1.7 KiB
C
/*
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* Copyright 2011 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <ns16550.h>
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#include <asm/io.h>
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#include <nand.h>
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#include <asm/fsl_law.h>
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#include <asm/fsl_ddr_sdram.h>
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const static u32 sysclk_tbl[] = {
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66666000, 7499900, 83332500, 8999900,
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99999000, 11111000, 12499800, 13333200
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};
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void board_init_f(ulong bootflag)
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{
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int px_spd;
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u32 plat_ratio, sys_clk, bus_clk;
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ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
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#if defined(CONFIG_SYS_NAND_BR_PRELIM) && defined(CONFIG_SYS_NAND_OR_PRELIM)
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set_lbc_br(0, CONFIG_SYS_NAND_BR_PRELIM);
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set_lbc_or(0, CONFIG_SYS_NAND_OR_PRELIM);
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#endif
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/* for FPGA */
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set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
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set_lbc_or(2, CONFIG_SYS_OR2_PRELIM);
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/* initialize selected port with appropriate baud rate */
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px_spd = in_8((unsigned char *)(PIXIS_BASE + PIXIS_SPD));
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sys_clk = sysclk_tbl[px_spd & PIXIS_SPD_SYSCLK_MASK];
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plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
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bus_clk = sys_clk * plat_ratio / 2;
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NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
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bus_clk / 16 / CONFIG_BAUDRATE);
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puts("\nNAND boot... ");
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/* copy code to RAM and jump to it - this should not return */
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/* NOTE - code has to be copied out of NAND buffer before
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* other blocks can be read.
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*/
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relocate_code(CONFIG_SPL_RELOC_STACK, 0,
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CONFIG_SPL_RELOC_TEXT_BASE);
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}
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void board_init_r(gd_t *gd, ulong dest_addr)
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{
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puts("\nSecond program loader running in sram...");
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nand_boot();
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}
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void putc(char c)
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{
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if (c == '\n')
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NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r');
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NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c);
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}
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void puts(const char *str)
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{
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while (*str)
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putc(*str++);
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}
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