mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-14 08:57:58 +00:00
1a4596601f
Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com>
563 lines
13 KiB
C
563 lines
13 KiB
C
/*
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* (C) Copyright 2006-2008
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* Texas Instruments, <www.ti.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _CPU_H
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#define _CPU_H
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#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
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#include <asm/types.h>
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#endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */
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/* Register offsets of common modules */
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/* Control */
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#ifndef __KERNEL_STRICT_NAMES
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#ifndef __ASSEMBLY__
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struct ctrl {
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u8 res1[0xC0];
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u16 gpmc_nadv_ale; /* 0xC0 */
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u16 gpmc_noe; /* 0xC2 */
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u16 gpmc_nwe; /* 0xC4 */
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u8 res2[0x22A];
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u32 status; /* 0x2F0 */
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u32 gpstatus; /* 0x2F4 */
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u8 res3[0x08];
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u32 rpubkey_0; /* 0x300 */
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u32 rpubkey_1; /* 0x304 */
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u32 rpubkey_2; /* 0x308 */
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u32 rpubkey_3; /* 0x30C */
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u32 rpubkey_4; /* 0x310 */
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u8 res4[0x04];
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u32 randkey_0; /* 0x318 */
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u32 randkey_1; /* 0x31C */
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u32 randkey_2; /* 0x320 */
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u32 randkey_3; /* 0x324 */
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u8 res5[0x124];
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u32 ctrl_omap_stat; /* 0x44C */
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};
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#else /* __ASSEMBLY__ */
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#define CONTROL_STATUS 0x2F0
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#endif /* __ASSEMBLY__ */
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#endif /* __KERNEL_STRICT_NAMES */
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#ifndef __KERNEL_STRICT_NAMES
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#ifndef __ASSEMBLY__
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struct ctrl_id {
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u8 res1[0x4];
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u32 idcode; /* 0x04 */
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u32 prod_id; /* 0x08 */
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u32 sku_id; /* 0x0c */
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u8 res2[0x08];
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u32 die_id_0; /* 0x18 */
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u32 die_id_1; /* 0x1C */
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u32 die_id_2; /* 0x20 */
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u32 die_id_3; /* 0x24 */
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};
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#endif /* __ASSEMBLY__ */
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#endif /* __KERNEL_STRICT_NAMES */
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/* device type */
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#define DEVICE_MASK (0x7 << 8)
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#define SYSBOOT_MASK 0x1F
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#define TST_DEVICE 0x0
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#define EMU_DEVICE 0x1
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#define HS_DEVICE 0x2
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#define GP_DEVICE 0x3
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/* device speed */
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#define SKUID_CLK_MASK 0xf
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#define SKUID_CLK_600MHZ 0x0
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#define SKUID_CLK_720MHZ 0x8
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#define GPMC_BASE (OMAP34XX_GPMC_BASE)
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#define GPMC_CONFIG_CS0 0x60
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#define GPMC_CONFIG_CS0_BASE (GPMC_BASE + GPMC_CONFIG_CS0)
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#ifndef __KERNEL_STRICT_NAMES
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#ifndef __ASSEMBLY__
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struct gpmc_cs {
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u32 config1; /* 0x00 */
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u32 config2; /* 0x04 */
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u32 config3; /* 0x08 */
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u32 config4; /* 0x0C */
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u32 config5; /* 0x10 */
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u32 config6; /* 0x14 */
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u32 config7; /* 0x18 */
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u32 nand_cmd; /* 0x1C */
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u32 nand_adr; /* 0x20 */
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u32 nand_dat; /* 0x24 */
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u8 res[8]; /* blow up to 0x30 byte */
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};
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struct bch_res_0_3 {
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u32 bch_result_x[4];
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};
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struct gpmc {
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u8 res1[0x10];
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u32 sysconfig; /* 0x10 */
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u8 res2[0x4];
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u32 irqstatus; /* 0x18 */
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u32 irqenable; /* 0x1C */
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u8 res3[0x20];
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u32 timeout_control; /* 0x40 */
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u8 res4[0xC];
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u32 config; /* 0x50 */
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u32 status; /* 0x54 */
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u8 res5[0x8]; /* 0x58 */
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struct gpmc_cs cs[8]; /* 0x60, 0x90, .. */
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u8 res6[0x14]; /* 0x1E0 */
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u32 ecc_config; /* 0x1F4 */
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u32 ecc_control; /* 0x1F8 */
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u32 ecc_size_config; /* 0x1FC */
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u32 ecc1_result; /* 0x200 */
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u32 ecc2_result; /* 0x204 */
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u32 ecc3_result; /* 0x208 */
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u32 ecc4_result; /* 0x20C */
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u32 ecc5_result; /* 0x210 */
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u32 ecc6_result; /* 0x214 */
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u32 ecc7_result; /* 0x218 */
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u32 ecc8_result; /* 0x21C */
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u32 ecc9_result; /* 0x220 */
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u8 res7[0x1C]; /* fill up to 0x240 */
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struct bch_res_0_3 bch_result_0_3[7]; /* 0x240 */
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};
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/* Used for board specific gpmc initialization */
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extern struct gpmc *gpmc_cfg;
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#else /* __ASSEMBLY__ */
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#define GPMC_CONFIG1 0x00
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#define GPMC_CONFIG2 0x04
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#define GPMC_CONFIG3 0x08
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#define GPMC_CONFIG4 0x0C
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#define GPMC_CONFIG5 0x10
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#define GPMC_CONFIG6 0x14
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#define GPMC_CONFIG7 0x18
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#endif /* __ASSEMBLY__ */
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#endif /* __KERNEL_STRICT_NAMES */
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/* GPMC Mapping */
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#define FLASH_BASE 0x10000000 /* NOR flash, */
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/* aligned to 256 Meg */
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#define FLASH_BASE_SDPV1 0x04000000 /* NOR flash, */
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/* aligned to 64 Meg */
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#define FLASH_BASE_SDPV2 0x10000000 /* NOR flash, */
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/* aligned to 256 Meg */
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#define DEBUG_BASE 0x08000000 /* debug board */
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#define NAND_BASE 0x30000000 /* NAND addr */
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/* (actual size small port) */
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#define PISMO2_BASE 0x18000000 /* PISMO2 CS1/2 */
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#define ONENAND_MAP 0x20000000 /* OneNand addr */
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/* (actual size small port) */
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/* SMS */
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#ifndef __KERNEL_STRICT_NAMES
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#ifndef __ASSEMBLY__
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struct sms {
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u8 res1[0x10];
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u32 sysconfig; /* 0x10 */
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u8 res2[0x34];
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u32 rg_att0; /* 0x48 */
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u8 res3[0x84];
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u32 class_arb0; /* 0xD0 */
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};
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#endif /* __ASSEMBLY__ */
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#endif /* __KERNEL_STRICT_NAMES */
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#define BURSTCOMPLETE_GROUP7 (0x1 << 31)
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/* SDRC */
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#ifndef __KERNEL_STRICT_NAMES
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#ifndef __ASSEMBLY__
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struct sdrc_cs {
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u32 mcfg; /* 0x80 || 0xB0 */
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u32 mr; /* 0x84 || 0xB4 */
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u8 res1[0x4];
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u32 emr2; /* 0x8C || 0xBC */
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u8 res2[0x14];
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u32 rfr_ctrl; /* 0x84 || 0xD4 */
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u32 manual; /* 0xA8 || 0xD8 */
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u8 res3[0x4];
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};
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struct sdrc_actim {
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u32 ctrla; /* 0x9C || 0xC4 */
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u32 ctrlb; /* 0xA0 || 0xC8 */
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};
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struct sdrc {
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u8 res1[0x10];
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u32 sysconfig; /* 0x10 */
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u32 status; /* 0x14 */
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u8 res2[0x28];
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u32 cs_cfg; /* 0x40 */
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u32 sharing; /* 0x44 */
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u8 res3[0x18];
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u32 dlla_ctrl; /* 0x60 */
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u32 dlla_status; /* 0x64 */
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u32 dllb_ctrl; /* 0x68 */
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u32 dllb_status; /* 0x6C */
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u32 power; /* 0x70 */
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u8 res4[0xC];
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struct sdrc_cs cs[2]; /* 0x80 || 0xB0 */
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};
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/* EMIF4 */
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typedef struct emif4 {
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unsigned int emif_mod_id_rev;
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unsigned int sdram_sts;
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unsigned int sdram_config;
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unsigned int res1;
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unsigned int sdram_refresh_ctrl;
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unsigned int sdram_refresh_ctrl_shdw;
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unsigned int sdram_time1;
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unsigned int sdram_time1_shdw;
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unsigned int sdram_time2;
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unsigned int sdram_time2_shdw;
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unsigned int sdram_time3;
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unsigned int sdram_time3_shdw;
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unsigned char res2[8];
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unsigned int sdram_pwr_mgmt;
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unsigned int sdram_pwr_mgmt_shdw;
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unsigned char res3[32];
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unsigned int sdram_iodft_tlgc;
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unsigned char res4[128];
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unsigned int ddr_phyctrl1;
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unsigned int ddr_phyctrl1_shdw;
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unsigned int ddr_phyctrl2;
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} emif4_t;
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#endif /* __ASSEMBLY__ */
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#endif /* __KERNEL_STRICT_NAMES */
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#define DLLPHASE_90 (0x1 << 1)
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#define LOADDLL (0x1 << 2)
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#define ENADLL (0x1 << 3)
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#define DLL_DELAY_MASK 0xFF00
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#define DLL_NO_FILTER_MASK ((0x1 << 9) | (0x1 << 8))
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#define PAGEPOLICY_HIGH (0x1 << 0)
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#define SRFRONRESET (0x1 << 7)
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#define PWDNEN (0x1 << 2)
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#define WAKEUPPROC (0x1 << 26)
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#define DDR_SDRAM (0x1 << 0)
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#define DEEPPD (0x1 << 3)
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#define B32NOT16 (0x1 << 4)
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#define BANKALLOCATION (0x2 << 6)
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#define RAMSIZE_128 (0x40 << 8) /* RAM size in 2MB chunks */
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#define ADDRMUXLEGACY (0x1 << 19)
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#define CASWIDTH_10BITS (0x5 << 20)
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#define RASWIDTH_13BITS (0x2 << 24)
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#define BURSTLENGTH4 (0x2 << 0)
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#define CASL3 (0x3 << 4)
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#define SDRC_ACTIM_CTRL0_BASE (OMAP34XX_SDRC_BASE + 0x9C)
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#define SDRC_ACTIM_CTRL1_BASE (OMAP34XX_SDRC_BASE + 0xC4)
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#define ARE_ARCV_1 (0x1 << 0)
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#define ARCV (0x4e2 << 8) /* Autorefresh count */
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#define OMAP34XX_SDRC_CS0 0x80000000
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#define OMAP34XX_SDRC_CS1 0xA0000000
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#define CMD_NOP 0x0
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#define CMD_PRECHARGE 0x1
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#define CMD_AUTOREFRESH 0x2
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#define CMD_ENTR_PWRDOWN 0x3
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#define CMD_EXIT_PWRDOWN 0x4
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#define CMD_ENTR_SRFRSH 0x5
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#define CMD_CKE_HIGH 0x6
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#define CMD_CKE_LOW 0x7
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#define SOFTRESET (0x1 << 1)
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#define SMART_IDLE (0x2 << 3)
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#define REF_ON_IDLE (0x1 << 6)
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/* DMA */
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#ifndef __KERNEL_STRICT_NAMES
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#ifndef __ASSEMBLY__
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struct dma4_chan {
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u32 ccr;
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u32 clnk_ctrl;
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u32 cicr;
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u32 csr;
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u32 csdp;
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u32 cen;
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u32 cfn;
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u32 cssa;
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u32 cdsa;
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u32 csel;
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u32 csfl;
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u32 cdel;
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u32 cdfl;
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u32 csac;
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u32 cdac;
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u32 ccen;
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u32 ccfn;
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u32 color;
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};
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struct dma4 {
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u32 revision;
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u8 res1[0x4];
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u32 irqstatus_l[0x4];
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u32 irqenable_l[0x4];
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u32 sysstatus;
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u32 ocp_sysconfig;
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u8 res2[0x34];
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u32 caps_0;
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u8 res3[0x4];
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u32 caps_2;
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u32 caps_3;
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u32 caps_4;
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u32 gcr;
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u8 res4[0x4];
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struct dma4_chan chan[32];
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};
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#endif /*__ASSEMBLY__ */
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#endif /* __KERNEL_STRICT_NAMES */
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/* timer regs offsets (32 bit regs) */
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#ifndef __KERNEL_STRICT_NAMES
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#ifndef __ASSEMBLY__
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struct gptimer {
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u32 tidr; /* 0x00 r */
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u8 res[0xc];
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u32 tiocp_cfg; /* 0x10 rw */
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u32 tistat; /* 0x14 r */
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u32 tisr; /* 0x18 rw */
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u32 tier; /* 0x1c rw */
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u32 twer; /* 0x20 rw */
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u32 tclr; /* 0x24 rw */
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u32 tcrr; /* 0x28 rw */
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u32 tldr; /* 0x2c rw */
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u32 ttgr; /* 0x30 rw */
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u32 twpc; /* 0x34 r*/
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u32 tmar; /* 0x38 rw*/
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u32 tcar1; /* 0x3c r */
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u32 tcicr; /* 0x40 rw */
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u32 tcar2; /* 0x44 r */
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};
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#endif /* __ASSEMBLY__ */
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#endif /* __KERNEL_STRICT_NAMES */
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/* enable sys_clk NO-prescale /1 */
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#define GPT_EN ((0x0 << 2) | (0x1 << 1) | (0x1 << 0))
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/* Watchdog */
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#ifndef __KERNEL_STRICT_NAMES
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#ifndef __ASSEMBLY__
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struct watchdog {
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u8 res1[0x34];
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u32 wwps; /* 0x34 r */
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u8 res2[0x10];
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u32 wspr; /* 0x48 rw */
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};
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#endif /* __ASSEMBLY__ */
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#endif /* __KERNEL_STRICT_NAMES */
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#define WD_UNLOCK1 0xAAAA
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#define WD_UNLOCK2 0x5555
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/* PRCM */
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#define PRCM_BASE 0x48004000
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#ifndef __KERNEL_STRICT_NAMES
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#ifndef __ASSEMBLY__
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struct prcm {
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u32 fclken_iva2; /* 0x00 */
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u32 clken_pll_iva2; /* 0x04 */
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u8 res1[0x1c];
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u32 idlest_pll_iva2; /* 0x24 */
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u8 res2[0x18];
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u32 clksel1_pll_iva2 ; /* 0x40 */
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u32 clksel2_pll_iva2; /* 0x44 */
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u8 res3[0x8bc];
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u32 clken_pll_mpu; /* 0x904 */
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u8 res4[0x1c];
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u32 idlest_pll_mpu; /* 0x924 */
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u8 res5[0x18];
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u32 clksel1_pll_mpu; /* 0x940 */
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u32 clksel2_pll_mpu; /* 0x944 */
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u8 res6[0xb8];
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u32 fclken1_core; /* 0xa00 */
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u32 res_fclken2_core;
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u32 fclken3_core; /* 0xa08 */
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u8 res7[0x4];
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u32 iclken1_core; /* 0xa10 */
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u32 iclken2_core; /* 0xa14 */
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u32 iclken3_core; /* 0xa18 */
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u8 res8[0x24];
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u32 clksel_core; /* 0xa40 */
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u8 res9[0xbc];
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u32 fclken_gfx; /* 0xb00 */
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u8 res10[0xc];
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u32 iclken_gfx; /* 0xb10 */
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u8 res11[0x2c];
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u32 clksel_gfx; /* 0xb40 */
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u8 res12[0xbc];
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u32 fclken_wkup; /* 0xc00 */
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u8 res13[0xc];
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u32 iclken_wkup; /* 0xc10 */
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u8 res14[0xc];
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u32 idlest_wkup; /* 0xc20 */
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u8 res15[0x1c];
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u32 clksel_wkup; /* 0xc40 */
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u8 res16[0xbc];
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u32 clken_pll; /* 0xd00 */
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u32 clken2_pll; /* 0xd04 */
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u8 res17[0x18];
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u32 idlest_ckgen; /* 0xd20 */
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u32 idlest2_ckgen; /* 0xd24 */
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u8 res18[0x18];
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u32 clksel1_pll; /* 0xd40 */
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u32 clksel2_pll; /* 0xd44 */
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u32 clksel3_pll; /* 0xd48 */
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u32 clksel4_pll; /* 0xd4c */
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u32 clksel5_pll; /* 0xd50 */
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u8 res19[0xac];
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u32 fclken_dss; /* 0xe00 */
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u8 res20[0xc];
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u32 iclken_dss; /* 0xe10 */
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u8 res21[0x2c];
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u32 clksel_dss; /* 0xe40 */
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u8 res22[0xbc];
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u32 fclken_cam; /* 0xf00 */
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u8 res23[0xc];
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u32 iclken_cam; /* 0xf10 */
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u8 res24[0x2c];
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u32 clksel_cam; /* 0xf40 */
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u8 res25[0xbc];
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u32 fclken_per; /* 0x1000 */
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u8 res26[0xc];
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u32 iclken_per; /* 0x1010 */
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u8 res27[0x2c];
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u32 clksel_per; /* 0x1040 */
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u8 res28[0xfc];
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u32 clksel1_emu; /* 0x1140 */
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u8 res29[0x2bc];
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u32 fclken_usbhost; /* 0x1400 */
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u8 res30[0xc];
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u32 iclken_usbhost; /* 0x1410 */
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};
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#else /* __ASSEMBLY__ */
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#define CM_CLKSEL_CORE 0x48004a40
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#define CM_CLKSEL_GFX 0x48004b40
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#define CM_CLKSEL_WKUP 0x48004c40
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#define CM_CLKEN_PLL 0x48004d00
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#define CM_CLKSEL1_PLL 0x48004d40
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#define CM_CLKSEL1_EMU 0x48005140
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#endif /* __ASSEMBLY__ */
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#endif /* __KERNEL_STRICT_NAMES */
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#define PRM_BASE 0x48306000
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#ifndef __KERNEL_STRICT_NAMES
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#ifndef __ASSEMBLY__
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struct prm {
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u8 res1[0xd40];
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u32 clksel; /* 0xd40 */
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u8 res2[0x50c];
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u32 rstctrl; /* 0x1250 */
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u8 res3[0x1c];
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u32 clksrc_ctrl; /* 0x1270 */
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};
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#endif /* __ASSEMBLY__ */
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#endif /* __KERNEL_STRICT_NAMES */
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#define PRM_RSTCTRL 0x48307250
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#define PRM_RSTCTRL_RESET 0x04
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#define PRM_RSTST 0x48307258
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#define PRM_RSTST_WARM_RESET_MASK 0x7D2
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#define SYSCLKDIV_1 (0x1 << 6)
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#define SYSCLKDIV_2 (0x1 << 7)
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#define CLKSEL_GPT1 (0x1 << 0)
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#define EN_GPT1 (0x1 << 0)
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#define EN_32KSYNC (0x1 << 2)
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#define ST_WDT2 (0x1 << 5)
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#define ST_MPU_CLK (0x1 << 0)
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#define ST_CORE_CLK (0x1 << 0)
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#define ST_PERIPH_CLK (0x1 << 1)
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#define ST_IVA2_CLK (0x1 << 0)
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#define RESETDONE (0x1 << 0)
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#define TCLR_ST (0x1 << 0)
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#define TCLR_AR (0x1 << 1)
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#define TCLR_PRE (0x1 << 5)
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/* SMX-APE */
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#define PM_RT_APE_BASE_ADDR_ARM (SMX_APE_BASE + 0x10000)
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#define PM_GPMC_BASE_ADDR_ARM (SMX_APE_BASE + 0x12400)
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#define PM_OCM_RAM_BASE_ADDR_ARM (SMX_APE_BASE + 0x12800)
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#define PM_IVA2_BASE_ADDR_ARM (SMX_APE_BASE + 0x14000)
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#ifndef __KERNEL_STRICT_NAMES
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#ifndef __ASSEMBLY__
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struct pm {
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u8 res1[0x48];
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u32 req_info_permission_0; /* 0x48 */
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u8 res2[0x4];
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u32 read_permission_0; /* 0x50 */
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u8 res3[0x4];
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u32 wirte_permission_0; /* 0x58 */
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u8 res4[0x4];
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u32 addr_match_1; /* 0x58 */
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u8 res5[0x4];
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u32 req_info_permission_1; /* 0x68 */
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u8 res6[0x14];
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u32 addr_match_2; /* 0x80 */
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};
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#endif /*__ASSEMBLY__ */
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#endif /* __KERNEL_STRICT_NAMES */
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/* Permission values for registers -Full fledged permissions to all */
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#define UNLOCK_1 0xFFFFFFFF
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#define UNLOCK_2 0x00000000
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#define UNLOCK_3 0x0000FFFF
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#define NOT_EARLY 0
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/* I2C base */
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#define I2C_BASE1 (OMAP34XX_CORE_L4_IO_BASE + 0x70000)
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#define I2C_BASE2 (OMAP34XX_CORE_L4_IO_BASE + 0x72000)
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#define I2C_BASE3 (OMAP34XX_CORE_L4_IO_BASE + 0x60000)
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/* MUSB base */
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#define MUSB_BASE (OMAP34XX_CORE_L4_IO_BASE + 0xAB000)
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/* OMAP3 GPIO registers */
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#define OMAP_GPIO_REVISION 0x0000
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#define OMAP_GPIO_SYSCONFIG 0x0010
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#define OMAP_GPIO_SYSSTATUS 0x0014
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#define OMAP_GPIO_IRQSTATUS1 0x0018
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#define OMAP_GPIO_IRQSTATUS2 0x0028
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#define OMAP_GPIO_IRQENABLE2 0x002c
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#define OMAP_GPIO_IRQENABLE1 0x001c
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#define OMAP_GPIO_WAKE_EN 0x0020
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#define OMAP_GPIO_CTRL 0x0030
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#define OMAP_GPIO_OE 0x0034
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#define OMAP_GPIO_DATAIN 0x0038
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#define OMAP_GPIO_DATAOUT 0x003c
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#define OMAP_GPIO_LEVELDETECT0 0x0040
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#define OMAP_GPIO_LEVELDETECT1 0x0044
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#define OMAP_GPIO_RISINGDETECT 0x0048
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#define OMAP_GPIO_FALLINGDETECT 0x004c
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#define OMAP_GPIO_DEBOUNCE_EN 0x0050
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#define OMAP_GPIO_DEBOUNCE_VAL 0x0054
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#define OMAP_GPIO_CLEARIRQENABLE1 0x0060
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#define OMAP_GPIO_SETIRQENABLE1 0x0064
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#define OMAP_GPIO_CLEARWKUENA 0x0080
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#define OMAP_GPIO_SETWKUENA 0x0084
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#define OMAP_GPIO_CLEARDATAOUT 0x0090
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#define OMAP_GPIO_SETDATAOUT 0x0094
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#endif /* _CPU_H */
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