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https://github.com/AsahiLinux/u-boot
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4a9e89a3e3
Allwinner seems to typically stick to a common MMIO memory map for several SoCs, but from time to time does some breaking changes, which also introduce new generations of some peripherals. The last time this happened with the H6, which apart from re-organising the base addresses also changed the clock controller significantly. We added a CONFIG_SUN50I_GEN_H6 symbol back then to mark SoCs sharing those traits. Now the Allwinner D1 changes the memory map again, and also extends the pincontroller, among other peripherals. To mark this generation of SoCs, add a CONFIG_SUNXI_GEN_NCAT2 symbol, this name is reportedly used in the Allwinner BSP code, and prevents us from inventing our own name. Add this new symbol to some guards that were already checking for the H6 generation, since many features are shared between the two (like the renovated clock controller). This paves the way to introduce a first user of this generation. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Tested-by: Samuel Holland <samuel@sholland.org>
87 lines
1.7 KiB
C
87 lines
1.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2007-2011
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* Allwinner Technology Co., Ltd. <www.allwinnertech.com>
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* Tom Cubie <tangliang@allwinnertech.com>
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*
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* Configuration settings for the Allwinner A10-evb board.
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*/
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#ifndef _SUNXI_TIMER_H_
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#define _SUNXI_TIMER_H_
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#ifndef __ASSEMBLY__
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#include <linux/types.h>
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#include <asm/arch/watchdog.h>
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/* General purpose timer */
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struct sunxi_timer {
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u32 ctl;
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u32 inter;
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u32 val;
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u8 res[4];
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};
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/* Audio video sync*/
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struct sunxi_avs {
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u32 ctl; /* 0x80 */
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u32 cnt0; /* 0x84 */
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u32 cnt1; /* 0x88 */
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u32 div; /* 0x8c */
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};
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/* 64 bit counter */
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struct sunxi_64cnt {
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u32 ctl; /* 0xa0 */
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u32 lo; /* 0xa4 */
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u32 hi; /* 0xa8 */
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};
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/* Rtc */
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struct sunxi_rtc {
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u32 ctl; /* 0x100 */
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u32 yymmdd; /* 0x104 */
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u32 hhmmss; /* 0x108 */
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};
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/* Alarm */
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struct sunxi_alarm {
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u32 ddhhmmss; /* 0x10c */
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u32 hhmmss; /* 0x110 */
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u32 en; /* 0x114 */
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u32 irqen; /* 0x118 */
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u32 irqsta; /* 0x11c */
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};
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/* Timer general purpose register */
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struct sunxi_tgp {
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u32 tgpd;
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};
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struct sunxi_timer_reg {
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u32 tirqen; /* 0x00 */
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u32 tirqsta; /* 0x04 */
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u8 res1[8];
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struct sunxi_timer timer[6]; /* We have 6 timers */
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u8 res2[16];
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struct sunxi_avs avs;
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#if defined(CONFIG_SUNXI_GEN_SUN4I) || defined(CONFIG_MACH_SUN8I_R40)
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struct sunxi_wdog wdog; /* 0x90 */
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/* XXX the following is not accurate for sun5i/sun7i */
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struct sunxi_64cnt cnt64; /* 0xa0 */
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u8 res4[0x58];
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struct sunxi_rtc rtc;
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struct sunxi_alarm alarm;
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struct sunxi_tgp tgp[4];
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u8 res5[8];
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u32 cpu_cfg;
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#elif defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_SUN50I_GEN_H6) || defined(CONFIG_SUNXI_GEN_NCAT2)
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u8 res3[16];
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struct sunxi_wdog wdog[5]; /* We have 5 watchdogs */
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#endif
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};
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#endif /* __ASSEMBLY__ */
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#endif
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