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b3e2d9fccb
Print reset state (warm/cold) together with the source (watchdog/MPU) which has triggered the warm reset on S10 & Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
46 lines
1.4 KiB
C
46 lines
1.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2016-2019 Intel Corporation <www.intel.com>
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*/
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#ifndef _RESET_MANAGER_SOC64_H_
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#define _RESET_MANAGER_SOC64_H_
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void reset_deassert_peripherals_handoff(void);
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int cpu_has_been_warmreset(void);
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void print_reset_info(void);
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void socfpga_bridges_reset(int enable);
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#define RSTMGR_SOC64_STATUS 0x00
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#define RSTMGR_SOC64_MPUMODRST 0x20
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#define RSTMGR_SOC64_PER0MODRST 0x24
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#define RSTMGR_SOC64_PER1MODRST 0x28
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#define RSTMGR_SOC64_BRGMODRST 0x2c
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#define RSTMGR_MPUMODRST_CORE0 0
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#define RSTMGR_PER0MODRST_OCP_MASK 0x0020bf00
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#define RSTMGR_BRGMODRST_DDRSCH_MASK 0X00000040
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#define RSTMGR_BRGMODRST_FPGA2SOC_MASK 0x00000004
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/* SDM, Watchdogs and MPU warm reset mask */
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#define RSTMGR_STAT_SDMWARMRST BIT(1)
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#define RSTMGR_STAT_MPU0RST_BITPOS 8
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#define RSTMGR_STAT_L4WD0RST_BITPOS 16
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#define RSTMGR_L4WD_MPU_WARMRESET_MASK (RSTMGR_STAT_SDMWARMRST | \
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GENMASK(RSTMGR_STAT_MPU0RST_BITPOS + 3, \
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RSTMGR_STAT_MPU0RST_BITPOS) | \
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GENMASK(RSTMGR_STAT_L4WD0RST_BITPOS + 3, \
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RSTMGR_STAT_L4WD0RST_BITPOS))
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/*
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* SocFPGA Stratix10 reset IDs, bank mapping is as follows:
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* 0 ... mpumodrst
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* 1 ... per0modrst
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* 2 ... per1modrst
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* 3 ... brgmodrst
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*/
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#define RSTMGR_L4WD0 RSTMGR_DEFINE(2, 0)
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#define RSTMGR_OSC1TIMER0 RSTMGR_DEFINE(2, 4)
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#define RSTMGR_UART0 RSTMGR_DEFINE(2, 16)
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#endif /* _RESET_MANAGER_SOC64_H_ */
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