u-boot/board/freescale/t208xrdb/t2080_pbi.cfg
Shengzhou Liu 8d67c3685e powerpc/t2080rdb: Add T2080PCIe-RDB board support
T2080PCIe-RDB is a Freescale Reference Design Board that hosts the T2080 SoC.
It works in two mode: standalone mode and PCIe endpoint mode.

T2080PCIe-RDB Feature Overview
------------------------------
Processor:
 - T2080 SoC integrating four 64-bit dual-threads e6500 cores up to 1.8GHz
DDR Memory:
 - Single memory controller capable of supporting DDR3 and DDR3-LP devices
 - 72bit 4GB DDR3-LP SODIMM in slot
Ethernet interfaces:
 - Two 10M/100M/1G RGMII ports on-board
 - Two 10Gbps SFP+ ports on-board
 - Two 10Gbps Base-T ports on-board
Accelerator:
 - DPAA components consist of FMan, BMan, QMan, PME, DCE and SEC
SerDes 16 lanes configuration:
 - SerDes-1 Lane A-B: to two 10G XFI fiber (MAC9 & MAC10)
 - SerDes-1 Lane C-D: to two 10G Base-T (MAC1 & MAC2)
 - SerDes-1 Lane E-H: to PCIe Goldfinger (PCIe4 x4, Gen3)
 - SerDes-2 Lane A-D: to PCIe Slot (PCIe1 x4, Gen2)
 - SerDes-2 Lane E-F: to C293 secure co-processor (PCIe2 x2)
 - SerDes-2 Lane G-H: to SATA1 & SATA2
IFC/Local Bus:
 - NOR:  128MB 16-bit NOR flash
 - NAND: 512MB 8-bit NAND flash
 - CPLD: for system controlling with programable header on-board
eSPI:
 - 64MB N25Q512 SPI flash
USB:
 - Two USB2.0 ports with internal PHY (both Type-A)
PCIe:
 - One PCIe x4 gold-finger
 - One PCIe x4 connector
 - One PCIe x2 end-point device (C293 Crypto co-processor)
SATA:
 - Two SATA 2.0 ports on-board
SDHC:
 - support a TF-card on-board
I2C:
 - Four I2C controllers.
UART:
 - Dual 4-pins UART serial ports

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-03-07 14:53:13 -08:00

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#
# Copyright 2013 Freescale Semiconductor, Inc.
#
# SPDX-License-Identifier: GPL-2.0+
#
# Refer doc/README.pblimage for more details about how-to configure
# and create PBL boot image
#
#PBI commands
#Initialize CPC1
09010000 00200400
09138000 00000000
091380c0 00000100
#512KB SRAM
09010100 00000000
09010104 fff80009
09010f00 08000000
#enable CPC1
09010000 80000000
#Configure LAW for CPC1
09000d00 00000000
09000d04 fff80000
09000d08 81000012
#Initialize eSPI controller, default configuration is slow for eSPI to
#load data, this configuration comes from u-boot eSPI driver.
09110000 80000403
09110020 2d170008
09110024 00100008
09110028 00100008
0911002c 00100008
#Errata for slowing down the MDC clock to make it <= 2.5 MHZ
094fc030 00008148
094fd030 00008148
#Configure alternate space
09000010 00000000
09000014 ff000000
09000018 81000000
#Flush PBL data
09138000 00000000
091380c0 00000000