mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-17 00:33:06 +00:00
352ed65df7
The M.2 slots of the related IOT2050 variant need to be configured according to the plugged cards. This tries to detect the card using the M.2 configuration pins of the B-key slot. If that fails, a U-Boot environment variable can be set to configure manually. This variable is write-permitted also in secure boot mode as it is not able to undermine the integrity of the booted system. The configuration is then applied to mux the serdes and to fix up the device tree passed to or loaded by the bootloader. The fix-ups are coming from device tree overlays that are embedded into the firmware image and there also integrity protected. The OS remains free to load a device tree to which they do not apply: U-Boot will not fail to boot in that case. Based on original patch by Chao Zeng. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
47 lines
1,001 B
Text
47 lines
1,001 B
Text
// SPDX-License-Identifier: GPL-2.0
|
|
/*
|
|
* IOT2050 M.2 variant, overlay for B-key USB3.0 + E-key PCIE1_LANE0
|
|
* Copyright (c) Siemens AG, 2022
|
|
*
|
|
* Authors:
|
|
* Chao Zeng <chao.zeng@siemens.com>
|
|
* Jan Kiszka <jan.kiszka@siemens.com>
|
|
*/
|
|
|
|
/dts-v1/;
|
|
/plugin/;
|
|
|
|
#include <dt-bindings/phy/phy.h>
|
|
#include <dt-bindings/gpio/gpio.h>
|
|
|
|
&serdes0 {
|
|
assigned-clock-parents = <&k3_clks 153 7>, <&k3_clks 153 4>;
|
|
};
|
|
|
|
&pcie0_rc {
|
|
status = "disabled";
|
|
};
|
|
|
|
&pcie1_rc {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&minipcie_pins_default>;
|
|
|
|
num-lanes = <1>;
|
|
phys = <&serdes1 PHY_TYPE_PCIE 0>;
|
|
phy-names = "pcie-phy0";
|
|
reset-gpios = <&wkup_gpio0 27 GPIO_ACTIVE_HIGH>;
|
|
status = "okay";
|
|
};
|
|
|
|
&dwc3_0 {
|
|
assigned-clock-parents = <&k3_clks 151 4>, /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */
|
|
<&k3_clks 151 8>; /* set PIPE3_TXB_CLK to WIZ8B2M4VSB */
|
|
phys = <&serdes0 PHY_TYPE_USB3 0>;
|
|
phy-names = "usb3-phy";
|
|
};
|
|
|
|
&usb0 {
|
|
maximum-speed = "super-speed";
|
|
snps,dis-u1-entry-quirk;
|
|
snps,dis-u2-entry-quirk;
|
|
};
|